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amd geode? nx processors data book amd geode? nx processors data book april 2006 publication id: 31177h
2 amd geode? nx processors data book ? 2006 advanced micro devices, inc. all rights reserved. the contents of this document are pr ovided in connection with advanced micro devices, inc. (?amd?) products. amd make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to s pecifications and produ ct descriptions at any time without notice. no license, whet her express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of mer- chantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intend ed, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd arrow logo, amd athlon, amd duron, and co mbinations thereof, geode, amd powernow!, and 3dnow! are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. mmx is a registered trademark of intel corporat ion in the u.s. and/or other jurisdictions. microsoft and windows are registered trademarks of microsoft co rporation in the united stat es and/or other jurisdictions. other product names used in this publication are for identific ation purposes only and may be trademarks of their respective companies.
amd geode? nx processors data book 3 contents 31177h contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 special features and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 interface signals architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.0 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2 connect and disconnect protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.3 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 sysclk multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.0 cpuid support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 v cca electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 5.4 v cc_core electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.7 open-drain test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.8 fid_change induced pll lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.9 thermal diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.10 signal and power-up requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.0 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1 die loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 opga package descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4 amd geode? nx processors data book contents 31177h appendix a supporting documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 a.1 thermal diode calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 a.2 conventions, abbreviations, and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 a.3 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
amd geode? nx processors data book 5 list of figures 31177h list of figures figure 1-1. typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2-1. logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2-2. processor pin diagram?topside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 2-3. processor pin diagram?bottomside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3-1. processor power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3-2. softvid transition during the amd proce ssor system bus disconnect for fid_change . 37 figure 3-3. amd processor system bus disconnect sequence in the stop grant state . . . . . . . . . . . . 38 figure 3-4. exiting the stop grant state and bus connect sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 3-5. northbridge connect state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 3-6. processor connect state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 5-1. v cc_core voltage waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 5-2. sysclk and sysclk# diffe rential clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 5-3. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 5-4. general ate open-drain test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 5-5. signal relationship requirements during power-up sequence . . . . . . . . . . . . . . . . . . . . . . 61 figure 6-1. 28104 opga package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 7-1. opn for the amd geode? nx processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6 amd geode? nx processors data book list of figures 31177h
amd geode? nx processors data book 7 list of tables 31177h list of tables table 2-1. pin assignment - sorted by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2-2. pin assignment - sorted alphabetically by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 2-3. softvid[4:0] and vid[4:0] code to voltage definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3-1. fid[4:0] sysclk multiplier combinat ions () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 3-2. processor special cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5-1. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5-2. v cca electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5-3. v cc_core electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5-4. voltage and frequency combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 5-5. sysclk and sysclk# dc characterist ics () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 5-6. softvid[4:0] and vid[4:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5-7. fid[3:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5-8. picd[1:0]# and picclk (apic pins) dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 5-9. amd processor system bus dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 5-10. general dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 5-11. sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 5-12. picd[1:0]# and picclk (apic pins) ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 5-13. amd processor system bus ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 5-14. general ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 5-15. fid_change induced pll lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 5-16. thermal diode electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 5-17. guidelines for platform thermal protection of the processor . . . . . . . . . . . . . . . . . . . . . . . . 59 table 5-18. thermal power performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 table 6-1. mechanical loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6-2. 28104 opga package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 7-1. valid opn combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table a-1. constants and variables for the ideal diode equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table a-2. temperature offset equation constants and variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table a-3. definitions of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table a-4. definitions of acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table a-5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8 amd geode? nx processors data book list of tables 31177h
amd geode? nx processors data book 9 1 overview 31177h *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w proces sor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark. 1.0 overview 1.1 general description the amd geode? nx 1750@14w processor*, amd geode nx 1500@6w processor*, and amd geode nx 1250@6w processor* (here after referred to as geode nx processor unless otherwise specified) were designed to power the next generation of embedded computing plat- forms, delivering extreme performance for windows ? xp, windows xpe, windows ce, and linux. the geode nx processor is manufactured using a 0.13 m process and provide industry-leading processing power for cutting-edge embedded applications. figure 1-1 shows a typical nx processor-based system block diagram. figure 1-1. typical system block diagram sdram or ddr memory bus agp pci bus lan pc card isa or lpc usb dual eide modem / audio battery agp bus thermal amd geode? nx processor programmable voltage regulator monitor amd processor system bus system controller (north bridge) peripheral bus controller (south bridge) docking controller super i/o
10 amd geode? nx processors data book overview 31177h the geode nx processor implements amd powernow!? technology, which achieves lower power states by adjusting the processor?s voltage and/or frequency. the nx 1500@6w* and nx 1250@6w* use fixed operating voltages, and are therefore only able to achieve lower power by adjusting the processor?s frequency, while the nx 1750@14w* can be adjusted in frequency and voltage for lower power operation. see section 5.4.1 "valid voltage and frequency combinations" on page 49 for more infor- mation. the geode nx processor is available in a low-pro- file, lidless organic pin grid array (opga) package. the geode nx processor features seventh-generation microarchitecture with integrated l2 cache that supports the growing processor and system bandwidth requirements of emerging software, graphics, i/o, and memory technolo- gies. the high-speed execution core in the processor includes multiple x86 instruction decoders, a dual-ported 128 kb split level-one (l1) cache (made up of a 64 kb l1 instruction cache and a 64 kb l1 data cache), a 256 kb l2 integrated cache, three independent integer pipelines, three address calculation pipelines, and a fully pipelined, out-of-order, floating-point engine. the processor?s microarch itecture supports amd 3dnow!? professional technology, a high-performance cache architecture, and the 266 mhz, 2.1 gb per second amd processor system bus. the amd processor system bus is designed to combine the latest technological advances, such as point-to-point topology, source-synchro- nous packet-based transfers, and low-voltage signaling, to provide an extremely powerful, scalable bus available for any x86 processor. the am d processor system bus oper- ates at twice the front side bus (fsb) frequency. the geode nx processor is binary-compatible with existing x86 software and backwards compatible with applications optimized for enhanced 3dnow!, mmx ? , and sse instruc- tions. using a data format and single-instruction multiple- data (simd) operations based on the mmx instruction model, the geode nx processor can produce as many as four, 32-bit, single-precision floating-point results per clock cycle. the implemented 3dnow! professional technology includes new integer multimed ia instructions and soft- ware-directed data movement instructions for optimizing such applications as streaming video for the internet, as well as new instructions for digital signal processing (dsp) and communications applications. 1.2 microarchitecture summary the following features summarize the geode nx proces- sor?s microarchitecture: advanced 0.13 m technology for higher frequency scaling and lower power consumption 128 kb l1 cache (made up of a 64 kb l1 instruction cache and a 64 kb l1 data cache) 256 kb l2 cache with hardware data prefetch pipelined floating-point execution unit that executes a peak of three x87 instructions per clock cycle support for mmx, sse, and 3dnow! professional instruction sets for high-performance multimedia instruc- tion processing dynamic transitions between higher performance and lower power processor performance states are supported by amd powernow! software and the windows ? xp operating system acpi 1.0b and acpi 2.0 compliant power management three out-of-order, superscalar, pipelined integer units three out-of-order, superscalar, pipelined address calculation units a 266 mhz amd processor system bus enabling leading-edge system bandwidth for data move- ment-intensive applications *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w proces sor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark.
amd geode? nx processors data book 11 overview 31177h 1.3 special features and requirements this data book provides the electrical, thermal and mechanical specifications for the amd geode nx proces- sor in the opga package. system builders have three choices when determining the optimal solution for their design needs: ? amd geode? nx 1250@6w processor* for value embedded applications requiring fanless performance. ? amd geode? nx 1500@6w processor* for fanless, high performance (up to 1ghz) with very low power consumption designs. ? amd geode? nx 1750@14w processor*, highest performance for demanding graphics, multimedia and high horsepower applications. the geode nx processor has some very important opera- tional conditions that the board designer must take into account. they include: ? a tighter processor core voltage tolerance is required for all negative excursions. a total tolerance of ?50 mv is required for the voltage delivered to the core of all versions of this processor. this dc tolerance is inclusive of any ac transients that may occur due to changing processor current requirements. see figure 5-1 "v cc_core voltage waveform" on page 48 for a graph- ical representation of this tole rance. proper output filter component layout is critical to achieving this tolerance at the higher loading of these processors. ? the geode nx processor has a 133 mhz fsb. by using both edges of the fsb clock, the processor is able to achieve a maximum of 266 million transfers per second (mtps) per data line for t he amd processor system bus. the increased speed of the fsb at low voltage places additional design constraint s on the implementation of the amd processor system bus. refer to the amd athlon? processor-based motherboard design guide (publication id 24363) and the amd geode? nx processors addendum to amd athlon? processor- based motherboard design guide (publication id 31860) for additional information on circuitry and layout guidelines required to fully support this processor. ? the geode nx processor supports the following ranges: ? the operational voltage for the nx 1250@6w processor* is fixed at 1.1v. ? the operational voltage for the nx 1500@6w processor* is fixed at 1.0v. ? the operational voltage range for the nx 1750@14w processor* is from 1.05v to 1.25v. specific imple- mentations may choose not to utilize the entire range due to other operational constraints. ? the geode nx processor has a 6x start-up multiplier. ? the geode nx processor is compatible with processor system boards that implem ent an fsb detect circuit. refer to the amd athlon? processor-based mother- board design guide (publication id 24363) and amd geode? nx processors addendum to amd athlon? processor-based motherboard design guide (publica- tion id 31860) for implementation details. di dt ---- - *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w proces sor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark.
12 amd geode? nx processors data book overview 31177h
amd geode? nx processors data book 13 2 signal definitions 31177h 2.0 signal definitions figure 2-1 is a logic symbol diagram for the amd geode? nx processor, showing the logical grouping of the input and out- put signals. figure 2-1. logic symbol diagram sdata[63:0]# sdatainclk[3:0]# sdataoutclk[3:0]# data saddin[14:2]# saddinclk# probe/syscmd saddout[14:2]# saddoutclk# vid[4:0] fid[3:0] a20m# clkfwdrst connect corefb corefb# ferr ignne # init# intr nmi procrdy pwrok reset# sfillvalid# smi# stpclk# sysclk# clock voltag e frequency legacy request amd geode? nx processor sdatainvalid# sdataoutvalid# power thermal diode thermda thermdc flush# softvid[4:0] fsb_sense front-side-bus picclk picd[1:0]# apic autodetect control control management & initialization (clkin# + rstclk#) sysclk# (clkin + rstclk)
14 amd geode? nx processors data book signal definitions 31177h 2.1 interface signals architecture the architecture is designed to deliver excellent data movement bandwidth for next-generation x86 platforms as well as the high-performance required by enterprise-class application software. the system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 64- bit bidirectional data channel), source-synchronous clock- ing, and a packet-based protocol. in addition, the system bus supports several control, clock, and legacy signals. the interface signals use an impedance controlled push-pull, low-voltage, swing-signaling technology con- tained within the socket a socket. for more information, see section 2.1.3 "amd processor system bus signals", section 2.3.4 "amd processor sys- tem bus interface signals" on page 26, and the amd athlon? processor system bus specification (publi- cation id 21902). 2.1.1 signaling technology the amd processor system bus uses a low-voltage, swing- signaling technology, that has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. the signals are push-pull and impedance compen- sated. the signal inputs us e differential receivers that require a reference voltage (v ref ). the reference signal is used by the receivers to determine if a signal is asserted or de-asserted by the source. termination resistors are not needed because the driver is impedance-matched to the circuit board and a high impedance reflection is used at the receiver to bring the signal past the input threshold. for more information about signals, see section 2.3 "sig- nal descriptions" on page 25. 2.1.2 push-pull (pp) drivers the amd geode nx processors support push-pull (pp) drivers. the system logic conf igures the proc essor with the configuration parameter called syspushpull (1 = pp). the impedance of the pp drivers is set to match the impedance of the circuit board by two external resistors connected to the zn and zp pins. see section 2.3.12 "power, ground and compensation circuit connections" on page 31 for more information. 2.1.3 amd processor system bus signals the amd processor system bus is a clock-forwarded, point-to-point interface with the following three point-to-point channels: ? a 13-bit unidirectional output address/command channel ? a 13-bit unidirectional input address/command channel ? a 72-bit bidirectional data channel for more information, see section 5.0 "electrical specifica- tions" on page 47 and the amd athlon? processor sys- tem bus specification (publication id 21902). 2.2 pin assignments this subsection defines the pin assignments: ? figure 2-2 on page 15 and figure 2-3 on page 16 shows the organic pin grid array (opga) for the geode nx processor, top and bottom views respectively. because some of the pin names are too long to fit in the grid, they are abbreviated. ? table 2-1 on page 17 lists all the pins sorted by pin number along with the abbreviation (where necessary) and some additional pin information. ? table 2-2 on page 23 is a quick reference and sorts the pins alphabetically by signal name (full name; no abbre- viation or other parameters are called out) with the corresponding pin number. pga orientation pins no pin is present at pin locations a1 and an1. circuit board designers should not allow for a pga socket pin at these locations. for more information, see the amd athlon? processor- based motherboard design guide (publication id 24363) and amd geode? nx processors addendum to amd athlon? processor-based motherboard design guide (publication id 31860).
amd geode? nx processors data book 15 signal definitions 31177h figure 2-2. processor pin diagram?topside view 12345 678910111213141516171819202122232425262728 293031323334353637 a sao12# sao5# sao3# sd55# sd61# sd53# sd63# sd62# nc sd57# sd39# sd35# sd34# sd44# nc sdoc2# sd40# sd30# a b v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc b c sao7# sao9# sao8# sao2# sd54# sdoc3# nc sd51# sd60# sd59# sd56# sd37# sd47# sd38# sd45# sd43# sd42# sd#41 sdoc1# c d v cc v cc v ss v cc v ss v cc v ss v cc vss vcc v ss v cc v ss vcc v ss v cc v ss v ss d e sao11# saoc# sao4# sao6# sd52# sd50# sd#49 sdic#3 sd#48 sd#58 sd#36 sd#46 nc sdic#2 sd33# sd32# nc sd31# sd22# e f v ss v ss v ss svid0 v ss v cc v ss v cc vss vcc v ss v cc v ss v cc nc v cc v cc v cc f g sao10# sao14# sao13# key key nc nc g15 key nc nc key key nc nc nc sd#20 sd#23 sd#21 g h v cc v cc svid2 svid3 svid4 v cc v ss v cc v ss v cc v ss v cc v ss nc nc nc v ss v ss h j sao0# sao1# nc vid4 amd geode? nx processor topside view nc sd19# sdic1# sd29# j k v ss v ss v ss svid1 nc v cc v cc v cc k l vid0 vid1 vid2 vid3 nc sd26# nc sd28# l m v cc v cc v cc v cc v ss v ss v ss v ss m n picclk picd0# picd1# key nc sd25# sd27# sd18# n p v ss v ss v ss v ss v cc v cc v cc v cc p q tck tms scnsn key nc sd24# sd17# sd16# q r v cc v cc v cc v cc v ss v ss v ss v ss r s scnck1 scninv scnck2 thda nc sd7# sd15# sd6# s t v ss v ss v ss v ss v cc v cc v cc v cc t u tdi trst# tdo thdc nc sd5# sd4# nc u v v cc v cc v cc v cc v ss v ss v ss v ss v w fid0 fid1 vref_s nc nc sdic#0 sd#2 sd#1 w x v ss v ss v ss v ss v cc v cc v cc v cc x y fid2 fid3 nc key nc nc sd3# sd12# y z v cc v cc v cc v cc v ss v ss v ss v ss z aa dbrdy dbreq# nc key nc sd8# sd0# sd13# aa ab v ss v ss v ss v ss v cc v cc v cc v cc ab ac stpc# pltst# zn nc nc sd10# sd14# sd11# ac ad v cc v cc v cc nc nc v ss v ss v ss ad ae a20m# pwrok zp nc nc sai5# sdoc0# sd9# ae af v ss v ss nc nc nc v ss v cc v ss v cc v ss v cc v ss v cc nc nc nc v cc v cc af ag ferr reset# nc key key corefb corefb# key key nc nc nc nc key key fsb sai2# sai11# sai7# ag ah v cc v cc amd nc v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss nc v ss v ss v ss ah aj ignne# init# vcc nc nc nc anlog nc nc nc clkfr v cca plbyp# nc sai0# sfillv# saic# sai6# sai3# aj ak v ss v ss cpr# nc v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss vcc v ss v cc v cc ak al intr flush# v cc nc nc nc plmn2 plbyc# clkin# rclk# k7co cnnct nc nc sai1# sdov# sai8# sai4# sai10# al am v cc v ss v ss nc v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss vcc v ss v cc v ss am an nmi smi# nc nc nc plmn1 plbyc clkin rclk k7co# prcrdy nc nc sai12# sai14# sdinv# sai13# sai9# an 12345 678910111213141516171819202122232425262728293031323334353637
16 amd geode? nx processors data book signal definitions 31177h figure 2-3. processor pin diagram?bottomside view abcdef ghjklmnpqrstuvwxyzaaabacadaeafagahajakalaman 1 sao7# sao11# sao10# sao0# vid0 picclk tck scnck1 tdi fid0 fid2 dbrdy stpc# a20m# ferr ignne# intr 1 2 v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc 2 3 sao12# sao9# saoc# sao14# sao1# vid1 picd0# tms scninv trst# fid1 fid3 dbreq# pltst# pwrok reset# init# flush# nmi 3 4 v cc v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss v ss 4 5 sao5# sao8# sao4# sao13# nc vid2 picd1# scnsn scnck2 tdo vref_s nc nc zn zp nc v cc v cc smi# 5 6 v ss v ss v ss svid2 v ss vcc vss v cc v ss v cc v ss v cc v ss v cc nc amd cpr# v ss 6 7 sao3# sao2# sao6# key vid4 vid3 key key thda thdc nc key key nc nc key nc nc nc 7 8 v cc v cc svid0 svid3 svid1 vcc vss v cc v ss v cc v ss v cc v ss nc nc nc nc nc 8 9 sd55# sd54# sd52# key amd geode? nx processor bottomside view key nc nc nc 9 10 v ss v ss v ss svid4 nc v cc v cc v cc 10 11 sd61# sdoc3# sd50# nc corefb nc nc nc 11 12 v cc v cc v cc v cc v ss v ss v ss v ss 12 13 sd53# nc sd49# nc corefb# anlog plmn2 plmn1 13 14 v ss v ss v ss v ss v cc v cc v cc v cc 14 15 sd63# sd51# sdic3# key key nc plbyc# plbyc 15 16 v cc v cc v cc v cc v ss v ss v ss v ss 16 17 sd62# sd60# sd48# key key nc clkin# clkin 17 18 v ss v ss v ss v ss v cc v cc v cc v cc 18 19 nc sd59# sd58# nc nc nc rclk# rclk 19 20 v cc v cc v cc v cc v ss v ss v ss v ss 20 21 sd57# sd56# sd36# nc nc clkfr k7co k7co# 21 22 v ss v ss v ss v ss v cc v cc v cc v cc 22 23 sd39# sd37# sd46# key nc vcca cnnct prcrdy 23 24 v cc v cc v cc v cc v ss v ss v ss v ss 24 25 sd35# sd47# nc key nc plbyp# nc nc 25 26 v ss v ss v ss v ss v cc v cc v cc v cc 26 27 sd34# sd38# sdic2# nc key nc nc nc 27 28 v cc v cc v cc nc nc v ss v ss v ss 28 29 sd44# sd45# sd33# nc key sai0# sai1# sai12# 29 30 v ss v ss nc nc nc v ss v cc v ss v cc v ss v cc v ss v cc nc nc nc v cc v cc 30 31 nc sd43# sd32# nc nc nc nc nc nc nc nc nc nc nc nc fsb sfillv# sdov# sai14# 31 32 v cc v cc v cc nc v cc v ss vcc vss v cc v ss v cc v ss v cc v ss nc v ss v ss v ss 32 33 sdoc2# sd42# nc sd20# sd19# sd26# sd25# sd24# sd7# sd5# sdic0# nc sd8# sd10# sai5# sai2# saic# sai8# sdinv# 33 34 v ss v ss v cc v ss v cc v ss vcc vss v cc v ss v cc v ss v cc v ss v cc v ss v cc v cc 34 35 sd40# sd41# sd31# sd23# sdic1# nc sd27# sd17# sd15# sd4# sd2# sd3# sd0# sd14# sdoc0# sai11# sai6# sai4# sai13# 35 36 v cc v ss v cc v ss v cc v ss vcc vss v cc v ss v cc v ss v cc v ss v cc v ss v cc v ss 36 37 sd30# sdoc1# sd22# sd21# sd29# sd28# sd18# sd16# sd6# nc sd1# sd12# sd13# sd11# sd9# sai7# sai3# sai10# sai9# 37 abcdef ghjklmnpqrstuvwxyzaaabacadaeafagahajakalaman
amd geode? nx processors data book 17 signal definitions 31177h table 2-1 cross-references socket a pin locations to signal names and is sorted by pin number. other table parame- ters are: ? signal name (abbreviation) column - the full signal name and the abbreviation name used in the pin diagrams (figure 2-2 on page 15 and figure 2-3 on page 16). ?level column - shows the electrical specification for this pin. ? ?p? indicates a push-pull mode driven by a single source. ? ?o? indicates open-drain mode that allows devices to share the pin. note: the geode nx processor supports push-pull driv- ers. for more information, see section 2.1.2 "push-pull (pp) drivers" on page 14. ?port column - shows the signal type: ? ?i? indicates input, ? ?o? indicates output, ? ?b? indicates bidirectional, ? ref. (reference) column - indicates if this signal should be referenced to v ss (g) or vcc_core (p) planes for the purpose of signal routing with respect to the current return paths. ? a ??? is used to indicate that the description is not appli- cable for the pin. table 2-1. pin assignment - sorted by pin number pin no. signal name (abbreviation) level port ref. a1 no pin - - - a3 saddout12# (sao12#) p o g a5 saddout5# (sao5#) p o g a7 saddout3# (sao3#) p o g a9 sdata55# (sd55#) p b p a11 sdata61# (sd61#) p b p a13 sdata53# (sd53#) p b g a15 sdata63# (sd63#) p b g a17 sdata62# (sd62#) p b g a19 nc pin - - - a21 sdata57# (sd57#) p b g a23 sdata39# (sd39#) p b g a25 sdata35# (sd35#) p b p a27 sdata34# (sd34#) p b p a29 sdata44# (sd44#) p b g a31 nc pin - - - a33 sdataoutclk2# (sdoc2#) p o p a35 sdata40# (sd40#) p b g a37 sdata30# (sd30#) p b p b2 v ss --- b4 v cc_core (v cc )--- b6 v ss --- b8 v cc_core (v cc )--- b10 v ss --- b12 v cc_core (v cc )--- b14 v ss --- b16 v cc_core (v cc )--- b18 v ss --- b20 v cc_core (v cc )--- b22 v ss --- b24 v cc_core (v cc )--- b26 v ss --- b28 v cc_core (v cc ) --- b30 v ss --- b32 v cc_core (v cc ) --- b34 v ss --- b36 v cc_core (v cc ) --- c1 saddout7# (sao7#) p o g c3 saddout9# (sao9#) p o g c5 saddout8# (sao8#) p o g c7 saddout2# (sao2#) p o g c9 sdata54# (sd54#) p b p c11 sdataoutclk3# (sdoc3#) p o g c13 nc pin - - - c15 sdata51# (sd51#) p b p c17 sdata60# (sd60#) p b g c19 sdata59# (sd59#) p b g c21 sdata56# (sd56#) p b g c23 sdata37# (sd37#) p b p c25 sdata47# (sd47#) p b g c27 sdata38# (sd38#) p b g c29 sdata45# (sd45#) p b g c31 sdata43# (sd43#) p b g c33 sdata42# (sd42) p b g c35 sdata41# (sd41#) p b g c37 sdataoutclk1# (sdoc1#) p o g d2 v cc_core (v cc ) --- d4 v cc_core (v cc ) --- d6 v ss --- d8 v cc_core (v cc ) --- d10 v ss --- d12 v cc_core (v cc ) --- pin no. signal name (abbreviation) level port ref.
18 amd geode? nx processors data book signal definitions 31177h d14 v ss --- d16 v cc_core (v cc )--- d18 v ss --- d20 v cc_core (v cc )--- d22 v ss --- d24 v cc_core (v cc )--- d26 v ss --- d28 v cc_core (v cc )--- d30 v ss --- d32 v cc_core (v cc )--- d34 v ss --- d36 v ss --- e1 saddout11# (sao11#) p o p e3 saddoutclk# (saoc#) p o g e5 saddout4# (sao4#) p o p e7 saddout6# (sao6#) p o g e9 sdata52# (sd52#) p b p e11 sdata50# (sd50#) p b p e13 sdata49# (sd49#) p b g e15 sdatainclk3# (sdic3#) p i g e17 sdata48# (sd48#) p b p e19 sdata58# (sd58#) p b g e21 sdata36# (sd36#) p b p e23 sdata46# (sd46#) p b p e25 nc pin - - - e27 sdatainclk2# (sdic2#) p i g e29 sdata33# (sd33#) p b p e31 sdata32# (sd32#) p b p e33 nc pin - - - e35 sdata31# (sd31#) p b p e37 sdata22# (sd22#) p b g f2 v ss --- f4 v ss --- f6 v ss --- f8 softvid0 (svid0) o o - f10 v ss --- f12 v cc_core (v cc )--- f14 v ss --- f16 v cc_core (v cc )--- f18 v ss --- f20 v cc_core (v cc )--- f22 v ss --- f24 v cc_core (v cc )--- f26 v ss --- pin no. signal name (abbreviation) level port ref. f28 v cc_core (v cc ) --- f30 nc pin - - - f32 v cc_core (v cc ) --- f34 v cc_core (v cc ) --- f36 v cc_core (v cc ) --- g1 saddout10# (sao10#) p o p g3 saddout14# (sao14#) p o g g5 saddout13# (sao13#) p o g g7key pin --- g9key pin --- g11 nc pin - - - g13 nc pin - - - g15key pin --- g17key pin --- g19 nc pin - - - g21 nc pin - - - g23key pin --- g25key pin --- g27 nc pin - - - g29 nc pin - - - g31 nc pin - - - g33 sdata20# (sd20#) p b g g35 sdata23# (sd23#) p b g g37 sdata21# (sd21#) p b g h2 v cc_core (v cc ) --- h4 v cc_core (v cc ) --- h6 softvid2 (svid2) o o - h8 softvid3 (svid3) o o - h10 softvid4 (svid4) o o - h12 v cc_core (v cc ) --- h14 v ss --- h16 v cc_core (v cc ) --- h18 v ss --- h20 v cc_core (v cc ) --- h22 v ss --- h24 v cc_core (v cc ) --- h26 v ss --- h28 nc pin - - - h30 nc pin - - - h32 nc pin - - - h34 v ss --- h36 v ss --- j1 saddout0# (sao0#) p o - j3 saddout1# (sao1#) p o - j5 nc pin - - - pin no. signal name (abbreviation) level port ref. table 2-1. pin assignment - sorted by pin number (continued)
amd geode? nx processors data book 19 signal definitions 31177h j7 vid4 o o - j31 nc pin - - - j33 sdata19# (sd19#) p b g j35 sdatainclk1# (sdic1#) p i p j37 sdata29# (sd29#) p b p k2 v ss --- k4 v ss --- k6 v ss --- k8 softvid1 (svid1) o o - k30 nc pin - - - k32 v cc_core (v cc )--- k34 v cc_core (v cc )--- k36 v cc_core (v cc )--- l1 vid0 o o - l3 vid1 o o - l5 vid2 o o - l7 vid3 o o - l31 nc pin - - - l33 sdata26# (sd26#) p b p l35 nc pin - - - l37 sdata28# (sd28#) p b p m2 v cc_core (v cc )--- m4 v cc_core (v cc )--- m6 v cc_core (v cc )--- m8 v cc_core (v cc )--- m30 v ss --- m32 v ss --- m34 v ss --- m36 v ss --- n1 picclk 0 i - n3 picd0# 0 b - n5 picd1# 0 b - n7 key pin - - - n31 nc pin - - - n33 sdata25# (sd25#) p b p n35 sdata27# (sd27#) p b p n37 sdata18# (sd18#) p b g p2 v ss --- p4 v ss --- p6 v ss --- p8 v ss --- p30 v cc_core (v cc )--- p32 v cc_core (v cc )--- p34 v cc_core (v cc )--- p36 v cc_core (v cc )--- pin no. signal name (abbreviation) level port ref. q1 tck p i - q3 tms p i - q5 scanshiften (scnsn) p i - q7key pin --- q31 nc pin - - - q33 sdata24# (sd24#) p b p q35 sdata17# (sd17#) p b g q37 sdata16# (sd16#) p b g r2 v cc_core (v cc ) --- r4 v cc_core (v cc ) --- r6 v cc_core (v cc ) --- r8 v cc_core (v cc ) --- r30 v ss --- r32 v ss --- r34 v ss --- r36 v ss --- s1 scanclk1 (scnck1) p i - s3 scaninteval (scninv) p i - s5 scanclk2 (scnck2) p i - s7 thermda (thda) - - - s31 nc pin - - - s33 sdata7# (sd7#) p b g s35 sdata15# (sd15#) p b p s37 sdata6# (sd6#) p b g t2 v ss --- t4 v ss --- t6 v ss --- t8 v ss --- t30 v cc_core (v cc ) --- t32 v cc_core (v cc ) --- t34 v cc_core (v cc ) --- t36 v cc_core (v cc ) --- u1 tdi p i - u3 trst# p i - u5 tdo p o - u7 thermdc (thdc) - - - u31 nc pin - - - u33 sdata5# (sd5#) p b g u35 sdata4# (sd4#) p b g u37 nc pin - - - v2 v cc_core (v cc ) --- v4 v cc_core (v cc ) --- v6 v cc_core (v cc ) --- v8 v cc_core (v cc ) --- v30 v ss --- pin no. signal name (abbreviation) level port ref. table 2-1. pin assignment - sorted by pin number (continued)
20 amd geode? nx processors data book signal definitions 31177h v32 v ss --- v34 v ss --- v36 v ss --- w1 fid0 o o - w3 fid1 o o - w5 vref_sys (vref_s) - i - w7 nc pin - - - w31 nc pin - - - w33 sdatainclk0# (sdic0#) p i g w35 sdata2# (sd2#) p b g w37 sdata1# (sd1#) p b p x2 v ss --- x4 v ss --- x6 v ss --- x8 v ss --- x30 v cc_core (v cc )--- x32 v cc_core (v cc )--- x34 v cc_core (v cc )--- x36 v cc_core (v cc )--- y1 fid2 o o - y3 fid3 o o - y5 nc pin - - - y7 key pin - - - y31 nc pin - - - y33 nc pin - - - y35 sdata3# (sd3#) p b g y37 sdata12# (sd12#) p b p z2 v cc_core (v cc )--- z4 v cc_core (v cc )--- z6 v cc_core (v cc )--- z8 v cc_core (v cc )--- z30 v ss --- z32 v ss --- z34 v ss --- z36 v ss --- aa1 dbrdy p o - aa3 dbreq# p i - aa5 nc pin - - - aa7 key pin - - - aa31 nc pin - - - aa33 sdata8# (sd8#) p b p aa35 sdata0# (sd0#) p b g aa37 sdata13# (sd13#) p b g ab2 v ss --- ab4 v ss --- pin no. signal name (abbreviation) level port ref. ab6 v ss --- ab8 v ss --- ab30 v cc_core (v cc ) --- ab32 v cc_core (v cc ) --- ab34 v cc_core (v cc ) --- ab36 v cc_core (v cc ) --- ac1 stpclk# (stpc#) p i - ac3 plltest# (pltst#) p i - ac5 zn p - - ac7 nc pin - - - ac31 nc pin - - - ac33 sdata10# (sd10#) p b p ac35 sdata14# (sd14#) p b g ac37 sdata11# (sd11#) p b g ad2 v cc_core (v cc ) --- ad4 v cc_core (v cc ) --- ad6 v cc_core (v cc ) --- ad8 nc pin - - - ad30 nc pin - - - ad32 v ss --- ad34 v ss --- ad36 v ss --- ae1 a20m# p i - ae3 pwrok p i - ae5 zp p - - ae7 nc pin - - - ae31 nc pin - - - ae33 saddin5# (sai5#) p i g ae35 sdataoutclk0# (sdoc0#) p o p ae37 sdata9# (sd9#) p b g af2 v ss --- af4 v ss --- af6 nc pin - - - af8 nc pin - - - af10 nc pin - - - af12 v ss --- af14 v cc_core (v cc ) --- af16 v ss --- af18 v cc_core (v cc ) --- af20 v ss --- af22 v cc_core (v cc ) --- af24 v ss --- af26 v cc_core (v cc ) --- af28 nc pin - - - af30 nc pin - - - pin no. signal name (abbreviation) level port ref. table 2-1. pin assignment - sorted by pin number (continued)
amd geode? nx processors data book 21 signal definitions 31177h af32 nc pin - - - af34 v cc_core (v cc )--- af36 v cc_core (v cc )--- ag1 ferr p o - ag3 reset# - i - ag5 nc pin - - - ag7 key pin - - - ag9 key pin - - - ag11 corefb - - - ag13 corefb# - - - ag15 key pin - - - ag17 key pin - - - ag19 nc pin - - - ag21 nc pin - - - ag23 nc pin - - - ag25 nc pin - - - ag27 key pin - - - ag29 key pin - - - ag31 fsb_sense (fsb) - o g ag33 saddin2# (sai2#) p i g ag35 saddin11# (sai11#) p i g ag37 saddin7# (sai7#) p i p ah2 v cc_core (v cc )--- ah4 v cc_core (v cc )--- ah6 amd pin - - - ah8 nc pin - - - ah10 v cc_core (v cc )--- ah12 v ss --- ah14 v cc_core (v cc )--- ah16 v ss --- ah18 v cc_core (v cc )--- ah20 v ss --- ah22 v cc_core (v cc )--- ah24 v ss --- ah26 v cc_core (v cc )--- ah28 v ss --- ah30 nc pin - - - ah32 v ss --- ah34 v ss --- ah36 v ss --- aj1 ignne# p i - aj3 init# p i - aj5 v cc_core (v cc )--- aj7 nc pin - - - aj9 nc pin - - - pin no. signal name (abbreviation) level port ref. aj11 nc pin - - - aj13 analog (anlog) - - - aj15 nc pin - - - aj17 nc pin - - - aj19 nc pin - - - aj21 clkfwdrst (clkfr) p i p aj23 v cca --- aj25 pllbypass# (plbyp#) p i - aj27 nc pin - - - aj29 saddin0# (sai0#) p i - aj31 sfillvalid# (sfillv#) p i g aj33 saddinclk# (saic#) p i g aj35 saddin6# (sai6#) p i p aj37 saddin3# (sai3#) p i g ak2 v ss --- ak4 v ss --- ak6 cpu_presence# (cpr#) - - - ak8 nc pin - - - ak10 v cc_core (v cc ) --- ak12 v ss --- ak14 v cc_core (v cc ) --- ak16 v ss --- ak18 v cc_core (v cc ) --- ak20 v ss --- ak22 v cc_core (v cc ) --- ak24 v ss --- ak26 v cc_core (v cc ) --- ak28 v ss --- ak30 v cc_core (v cc ) --- ak32 v ss --- ak34 v cc_core (v cc ) --- ak36 v cc_core (v cc ) --- al1 intr p i - al3 flush# p i - al5 v cc_core (v cc ) --- al7 nc pin - - - al9 nc pin - - - al11 nc pin - - - al13 pllmon2 (plmn2) o o - al15 pllbypassclk# (plbyc#) p i - al17 clkin# p i p al19 rstclk# (rclk#) p i p al21 k7clkout (k7co) p o - al23 connect (cnnct) p i p al25 nc pin - - - pin no. signal name (abbreviation) level port ref. table 2-1. pin assignment - sorted by pin number (continued)
22 amd geode? nx processors data book signal definitions 31177h al27 nc pin - - - al29 saddin1# (sai1#) p i - al31 sdataoutvalid# (sdov#) p i p al33 saddin8# (sai8#) p i p al35 saddin4# (sai4#) p i g al37 saddin10# (sai10#) p i g am2 v cc_core (v cc )--- am4 v ss --- am6 v ss --- am8 nc pin - - - am10 v cc_core (v cc )--- am12 v ss --- am14 v cc_core (v cc )--- am16 v ss --- am18 v cc_core (v cc )--- am20 v ss --- am22 v cc_core (v cc )--- am24 v ss --- am26 v cc_core (v cc )--- am28 v ss --- am30 v cc_core (v cc )--- am32 v ss --- am34 v cc_core (v cc )--- am36 v ss --- an1 no pin - - - an3 nmi p i - an5 smi# p i - an7 nc pin - - - an9 nc pin - - - an11 nc pin - - - an13 pllmon1 (plmn1) o b - pin no. signal name (abbreviation) level port ref. an15 pllbypassclk (plbyc) p i - an17 clkin p i p an19 rstclk (rclk) p i p an21 k7clkout# (k7co#) p o - an23 procrdy (prcrdy) p o p an25 nc pin - - - an27 nc pin - - - an29 saddin12# (sai12#) p i g an31 saddin14# (sai14#) p i g an33 sdatainvalid# (sdinv#) p i p an35 saddin13# (sai13#) p i g an37 saddin9# (sai9#) p i g pin no. signal name (abbreviation) level port ref. table 2-1. pin assignment - sorted by pin number (continued)
amd geode? nx processors data book 23 signal definitions 31177h table 2-2. pin assignment - sorted alphabetically by signal name signal name pin no. a20m# ae1 amd pin ah6 analog aj13 clkfwdrst aj21 clkin an17 clkin# al17 connect al23 corefb ag11 corefb# ag13 cpu_presence# ak6 dbrdy aa1 dbreq# aa3 ferr ag1 fid0 w1 fid1 w3 fid2 y1 fid3 y3 flush# al3 fsb_sense ag31 ignne# aj1 init# aj3 intr al1 k7clkout al21 k7clkout# an21 key pin (total of 16) g7, g9, g23, aa7, ag9, ag17, ag27, ag29, g15, g17, g25, n7, q7, y7, ag7, ag15 nc pin (total of 71) g11, j31, k30, n31, s31, u31, w7, w31, y5, y31, aa5, aa31, ac7, ac31, ad8, ad30, ae7, ae31, af6, af8, af10, af28, af30, af32, ag5, ag19, ag21, ag23, ag25, ah8, ah30, aj7, aj9, aj11, aj15, aj17, aj19, aj27, ak8, al7, al9, al11, al25, al27, am8, an7, an9, an11, an25, an27, a19, a31, c13, e25, e33, f30, g13, g19, g21, g27, g29, g31, h28, h30, h32, j5, l31, l35, q31, u37, y33 nmi an3 no pin a1, an1 picclk n1 picd0# n3 picd1# n5 pllbypass# aj25 pllbypassclk an15 pllbypassclk# al15 pllmon1 an13 pllmon2 al13 plltest# ac3 procrdy an23 pwrok ae3 reset# ag3 rstclk an19 rstclk# al19 saddin0# aj29 saddin1# al29 saddin2# ag33 saddin3# aj37 saddin4# al35 saddin5# ae33 saddin6# aj35 saddin7# ag37 saddin8# al33 saddin9# an37 saddin10# al37 saddin11# ag35 saddin12# an29 saddin13# an35 saddin14# an31 saddinclk# aj33 saddout0# j1 saddout1# j3 saddout2# c7 saddout3# a7 saddout4# e5 saddout5# a5 saddout6# e7 saddout7# c1 saddout8# c5 saddout9# c3 saddout10# g1 saddout11# e1 saddout12# a3 saddout13# g5 saddout14# g3 saddoutclk# e3 scanclk1 s1 signal name pin no. scanclk2 s5 scaninteval s3 scanshiften q5 sdata0# aa35 sdata1# w37 sdata2# w35 sdata3# y35 sdata4# u35 sdata5# u33 sdata6# s37 sdata7# s33 sdata8# aa33 sdata9# ae37 sdata10# ac33 sdata11# ac37 sdata12# y37 sdata13# aa37 sdata14# ac35 sdata15# s35 sdata16# q37 sdata17# q35 sdata18# n37 sdata19# j33 sdata20# g33 sdata21# g37 sdata22# e37 sdata23# g35 sdata24# q33 sdata25# n33 sdata26# l33 sdata27# n35 sdata28# l37 sdata29# j37 sdata30# a37 sdata31# e35 sdata32# e31 sdata33# e29 sdata34# a27 sdata35# a25 sdata36# e21 sdata37# c23 sdata38# c27 sdata39# a23 sdata40# a35 sdata41# c35 sdata42# c33 sdata43# c31 sdata44# a29 sdata45# c29 signal name pin no.
24 amd geode? nx processors data book signal definitions 31177h sdata46# e23 sdata47# c25 sdata48# e17 sdata49# e13 sdata50# e11 sdata51# c15 sdata52# e9 sdata53# a13 sdata54# c9 sdata55# a9 sdata56# c21 sdata57# a21 sdata58# e19 sdata59# c19 sdata60# c17 sdata61# a11 sdata62# a17 sdata63# a15 sdatainclk0# w33 sdatainclk1# j35 sdatainclk2# e27 sdatainclk3# e15 sdatainvalid# an33 sdataoutclk0# ae35 sdataoutclk1# c37 sdataoutclk2# a33 sdataoutclk3# c11 sdataoutvalid# al31 sfillvalid# aj31 smi# an5 softvid0 f8 softvid1 k8 softvid2 h6 softvid3 h8 softvid4 h10 stpclk# ac1 tck q1 tdi u1 tdo u5 thermda s7 thermdc u7 tms q3 trst# u3 signal name pin no. v cc_core (total of 101) b12, b16, b20, b28, b32, d2, d4, d8, d12, d16, d20, d24, d28, d32, f12, f16, f20, f24, f28, f32, f34, f36, h2, h4, h12, h16, h20, h24, k32, k34, k36, m2, m4, m6, m8, p30, p32, p34, p36, r2, r4, r6, r8, t30, t32, t34, t36, v2, v4, v6, v8, x30, x32, x34, x36, z2, z4, z6, z8, ab30, ab32, ab34, ab36, ad2, ad4, ad6, af14, af18, af22, af26, af34, af36, ah2, ah4, ah10, ah14, ah18, ah22, ah26, aj5, ak10, ak14, ak18, ak22, ak26, ak30, ak34, ak36, al5, am2, am10, am14, am18, am22, am26, am30, am34, b4, b8, b24, b36, v cca aj23 vid0 l1 vid1 l3 vid2 l5 vid3 l7 vid4 j7 vref_sys w5 signal name pin no. v ss (total of 101) b2, b6, b10, b14, b18, b22, b26, b30, b34, d6, d10, d14, d18, d22, d26, d30, d34, d36, f2, f4, f6, f10, f14, f18, f22, f26, h14, h18, h22, h26, h34, h36, k2, k4, k6, m30, m32, m34, m36, p2, p4, p6, p8, r30, r32, r34, r36, t2, t4, t6, t8, v30, v32, v34, v36, x2, x4, x6, x8, z30, z32, z34, z36, ab2, ab4, ab6, ab8, ad32, ad34, ad36, af2, af4, af12, af16, af20, af24, ah12, ah16, ah20, ah24, ah28, ah32, ah34, ah36, ak2, ak4, ak12, ak16, ak20, ak24, ak28, ak32, am4, am6, am12, am16, am20, am24, am28, am32, am36 zn ac5 zp ae5 signal name pin no. table 2-2. pin assignment - sorted alphabetically by signal name (continued)
amd geode? nx processors data book 25 signal definitions 31177h 2.3 signal descriptions 2.3.1 clock interface signals signal name pin no . port description sysclk -- -- system clock. sysclk and sysclk# are differential input clock signals provided to the pll of the processor from a system clock generator. see clkin and rstclk (sysclk) signal description. sysclk# -- -- clkin an17 i clock in and reset clock. connect clkin with rstclk and name it sysclk. connect clkin# with rstclk# and name it sysclk#. length match the clocks from the clock generator to the northbridge and processor. clkin# al17 i rstclk al19 i rstclk# al19 i k7clkout al21 o k7 clock output. these signals are each terminated with a resistor pair, 100 ohms to v cc_core and 100 ohms to v ss . the effective termination resistance and voltage are 50 ohms and v cc_core /2. route as short as possible from the processor pins. k7clkout# an21 o 2.3.2 power management and initialization interface signals signal name pin no . port description procrdy an23 o processor ready. an output from the system used for power man- agement and clock-forward initialization at reset. connect al23 i connect. an input from the system used for power management and clock-forward initialization at reset. clkfwdrst aj21 i clock forward reset. resets the clock-forward circuitry for both the system and processor. stpclk# ac1 i stop clock. an input that causes the processor to enter a lower power mode and issue a stop grant special cycle. reset# ag3 i reset. when asserted, reset# causes the initialization of all pro- cessor states and invalidates cache blocks without write back of previous data. cpu_presence ak6 -- cpu presence. cpu_presence# is connected to v ss on the processor package. if pulled up on the circuit board, it may be used to detect the presence or absence of a processor. 2.3.3 southbridge interface signals signal name pin no . port description ferr ag1 o floating point error. an output to the system that is asserted for any unmasked numerical exception independent of the ne bit in cr0. ferr is a totem-pole-driven active high signal that must be inverted and level shifted to an active low signal. for more information about ferr and ferr#, see the ?required circuits? chapter of the amd athlon? processor-based mother- board design guide (publication id 24363). ignne# aj1 i ignore numeric errors. when asserted, this signal tells the pro- cessor to ignore numeric errors.
26 amd geode? nx processors data book signal definitions 31177h init# aj3 i interrupt integer registers. when asserted, init # resets the inte- ger registers without affecting the floating point registers or the inter- nal caches. execution starts at 0ffff_fff0h intr al1 i interrupt. an input from the system th at causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. nmi an3 i non-maskable interrupt. an input from the system that causes a non-maskable interrupt. a20m# ae1 i address bit 20. an input from the system used to simulate address wrap-around in the 20-bit 8086. smi# an5 i system management interrupt. an input that causes the proces- sor to enter the system management mode. flush# al3 i flush. flush# must be tied to v cc_core with a pull-up resistor. if a debug connector is implemented, flush# is routed to the debug connector. 2.3.3 southbridge interface signals (continued) signal name pin no . port description 2.3.4 amd processor system bus interface signals signal name pin no . port description vref_sys w5 i system bus voltage reference. this input driv es the threshold voltage for the amd processor system bus input receivers. the value of vref_sys is system spec ific. in addition, to minimize v cc_core noise rejection from vref_sys, include decoupling capacitors. for more information, see the amd athlon? processor- based motherboard design guide (publication id 24363) and amd geode? nx processors addendum to amd athlon? processor- based motherboard design guide (publication id 31860). sdata[63:0]# see table 2-2 on page 23 b system data bus. bidirectional interface to and from the processor and system for data movement. data is skewed-alig ned with either the sdatainclk[3:0]# or sdataout clk[3:0]# signal. both rising and falling edges are used to transfer data. sdatainclk[3:0]# e15, e27, j35, w33 i system data input clock. the single-ended forwarded clock driven by the system to transfer data on sdata[63:0]#. each 16-bit data word is skewed-aligned with this clock. both rising and falling edges are used to transfer data. sdataoutclk[3:0] c11, a33, c37, ae35 o system data output clock. the single-ended forwarded clock driven by the system to transfer data on sdata[63:0]#. each 16-bit data word is skewed-aligned with this clock. both rising and falling edges are used to transfer data. sdatainvalid# an33 i system data input valid. this input is driven by the system and controls the flow of data into the processor. sdatainvalid# can be used to introduce an arbitrary number of cycles between octa- words into the processor. sdataoutvalid# al31 i system data output valid. this input is driven by the system and controls the flow of data from the processor. sdataoutvalid# can be used to introduce an arbitrary number of cycles between quadwords into the processor.
amd geode? nx processors data book 27 signal definitions 31177h sfillvalid# aj31 i system bus fill valid. when asserted, validates the current mem- ory or i/o data transfer into the processor. the system can tie this pin to the asserted state (validating all fills), or use it to enable or cancel fills as they progress. the processor can sample sfillvalid# at d0 or d1 (that is , the first or second data beat). saddin[14:2]# see table 2-2 on page 23 i system address inputs. the unidirectional system address and command interface into the processo r from the system. it is used to transfer probes or data movement commands into the processor. all probes and commands on saddin[14:2]# are skewed-aligned with the forward clock, saddinclk#. saddinclk# aj33 i system address input clock. the single-ended forwarded clock for saddin[14:2]# driven by the system. both rising and falling edges are used to transfer probes or commands. saddout[14:2]# see table 2-2 on page 23 i system address outputs. the unidirectio nal system address interface from the processor to the system. it is used to transfer pro- cessor commands or probe responses to the system. all commands on saddout[14:0#] are skewed-aligned with the forward clock saddoutclk#. saddoutclk# e3 i system address output clock. the single-ended forwarded clock for saddout[14:2]# driven by the processor. both rising and fall- ing edges are used to transfer commands or probe responses. saddin[1:0]# al29, aj29 system address inputs and outputs bits 1 and 0. the nx pro- cessor does not support saddin[ 1:0]# or saddout[1:0]#. sad- din[1]# is tied to v cc with pull-up resistors, if this bit is not supported by the northbridge. saddout[1:0]# are tied to v cc with pull-up resistors if these pins are supported by the northbridge. for more information, see the amd athlon? processor system bus specification (publication id 21902). saddout[1:0]# j3, j1 2.3.4 amd processor system bus interface signals (continued) signal name pin no . port description 2.3.5 apic interface signals signal name pin no . port description picclk n1 i apic clock and interrupts. the advanced programmable inter- rupt controller (apic) feature provides a flexible and expandable means of delivering interrupts in a system using an amd processor. picd[1:0]# are the bidirectional message passing signals used for the apic and are driven to the southbridge or a dedicated i/o apic. picclk must be driven with a valid clock input. refer to vcc_2.5v generation circuit, found in the section, ?moth- erboard required circuits? of the amd athlon? processor-based motherboard design guide (publication id 24363) for the required supporting circuity. for more information, see table 5-8 "picd[1:0]# and picclk (apic pins) dc characteristics" on page 52. picd[1:0]# n5, n3 b
28 amd geode? nx processors data book signal definitions 31177h 2.3.6 fsb interface signals signal name pin no . port description fsb_sense ag31 o front side bus sense. this signal may be used by an external cir- cuit to automatically detect the front side bus (fsb) setting of the processor. this pin is always pulled low by the package, indicating that the fsb of the processor is 133 mhz. the fsb_sense pin is 3.3v tolerant. 2.3.7 frequency id interface signals signal name pin no . port description fid[3:0] y3, y1, w3, w1 o frequency identifi cation outputs. after pwrok is asserted to the processor the fid[3:0] pins dr ive a value of: fid[3:0] = 0110 that corresponds to a 6x sysclk multiplier for the 133 mhz fsb. this information is used by the northbridge to create the sip (serial ini- tialization packet) stream that t he northbridge sends to the proces- sor after reset# is de-asserted. for more information, see sect ion 3.4 "sysclk multipliers" on page 42 and table 5-7 "fid[3:0] dc characteristics" on page 51. 2.3.8 thermal diode interface signals signal name pin no . port description thermda s7 -- thermal diode anode and cathode. these signals are used to monitor the actual temperature of the processor die, providing more accurate temperature control to the system. see table 5-16 "ther- mal diode electrical characteristics" on page 59 for more details. thermdc u7 -- 2.3.9 voltage control interface signals signal name pin no . port description corefb ag11 -- core feedback. these are outputs to the system that provide pro- cessor core voltage feedback to the system. corefb# ag13 -- pwrok ae3 i power okay. the pwrok input to the processor must not be asserted until all voltage planes in the system are within specifica- tion and all system clocks are ru nning within specification. for more information, section 5.10 "signal and power-up require- ments" on page 61.
amd geode? nx processors data book 29 signal definitions 31177h softvid[4:0] h10, h8, h6, k8, f8 o soft voltage id/voltage id mux. amd powernow!? technology can use the fid_change protocol described in section 4.1 on page 9 to transition the softvi d[4:0] outputs and therefore v cc_core as part of processor performance state transitions. note: the nx 1750@14w processor* supports multiple core volt- ages whereas the nx 1500@6w and nx 1250@6w pro- cessors* support only one core voltage (nx 1500@6w = 1.0v) (nx 1250@6w = 1.1v). the vid[4:0] (voltage id) and soft vid[4:0] (software driven volt- age id) outputs are used by the dc/dc power converter to select the processor core voltage. the vi d[4:0] pins are shorted to ground or left unconnected on the packa ge and must be pulled up on the circuit board. the softvid[4:0] pi ns are open-drain and 2.5v toler- ant. refer to the vcc_2.5v generation circuit found in the motherboard required circuits section of the amd athlon? processor-based motherboard design guide (publication id 24363) for the required supporting circuitry. the circuit board is required to implement a vid multiplexer to select a deterministic voltage for the processor at power-up before the pwrok input is asserted. before pwrok is asserted, the vid multiplexer drives the vid value from vid[4:0] pins to the dc/dc converter for v cc_core . after pwrok is asserted, the vid multi- plexer drives the vid value from the softvid[4:0] pins to the dc/dc converter for v cc_core of the processor. refer to the amd athlon? processor-based motherboard design guide (publi- cation id 24363) and the amd geode? nx processors addendum to amd athlon? processor-based motherboard design guide (publication id 31860) for the recommended vid multiplexer circuit. the softvid[4:0] pins are driven by the processor to select the maximum v cc_core of the processor as reported by the maximum vid field of the fidvidstatus msr (msr c001_0042h) within 20 ns of pwrok assertion. before pwrok is asserted, the softvid[4:0] outputs are not driven to a deterministic value. the softvid[4:0] outputs must be used to select v cc_core after pwrok is asserted. any time the reset# input is asserted, the softvid[4:0] pins will be driven to select the maximum voltage. note: the start-up vid and maximum vi d fields of the fidvidsta- tus msr report the same value that corresponds to the nominal voltage that the processor requires to operate at maximum frequency. amd powernow! technology can use the fid_change protocol described in section 3.1 "power management states" on page 33 to transition the softvid[4:0] outputs and therefore v cc_core as part of processor performance state transitions. the vid codes used by the processor are defined in table 2-3 "softvid[4:0] and vid[4:0] code to voltage definition" on page 30. *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w processor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark. vid[4:0] j7, l7, l5, l3, l1 o 2.3.9 voltage control interface signals (continued) signal name pin no . port description
30 amd geode? nx processors data book signal definitions 31177h table 2-3. softvid[4:0] and vid[4:0] code to voltage definition vid[4:0] v cc_core (v) vid[4:0] v cc_core (v) 00000 2.000 10000 1.275 00001 1.950 10001 1.250 00010 1.900 10010 1.225 00011 1.850 10011 1.200 00100 1.800 10100 1.175 00101 1.750 10101 1.150 00110 1.700 10110 1.125 00111 1.650 10111 1.100 01000 1.600 11000 1.075 01001 1.550 11001 1.050 01010 1.500 11010 1.025 01011 1.450 11011 1.000 01100 1.400 11100 0.975 01101 1.350 11101 0.950 01110 1.300 11110 0.925 01111 shutdown 11111 shutdown 2.3.10 test measurement interface signals signal name pin no . port description tck q1 i jtag interface pins. tck, tms, tdi, trst#, and tdo pins should be connected directly to the circuit board debug connector. pull up tdi, tck, tms, and trst# to v cc_core with pull-up resis- tors. tms q3 i tdi u1 i trst# u3 i tdo u5 o plltest# ac3 i pll bypass and test. these signals makeup the pll bypass and test interface. this interface is tied disabled on the circuit board. all six pin signals are routed to the debug connector. all four processor inputs (plltest#, pllbypass#, pllmon1, and pllmon2) are tied to v cc_core with pull-up resistors. pllbypass# aj25 i pllmon1 an13 b pllmon2 al13 o pllbypassclk an15 i pllbypassclk# al15 i dbrdy aa1 o debug ready and debug request. dbrdy and dbreq# are routed to the debug connector. dbreq# is tied to v cc_core with a pull-up resistor. dbreq# aa3 i scanshiften q5 i scan interface. this interface is amd internal and is tied disabled with pull-down resistors to ground on the circuit board. scaninteval s3 i scanclk1 s1 i scanclk2 s5 i
amd geode? nx processors data book 31 signal definitions 31177h 2.3.11 key pin, amd pin, anal og pin and no connect pins signal name pin no . port description key pins see table 2-2 on page 23 -- key pins (total of 16). these 16 locations are for processor type keying for forwards and backwards compatibility. circuit board designers should treat key pins like nc (no connect) pins. see the nc pins signal description for more information. a socket designer has the option of creating a top mold piece that allows pga key pins only where designated. howeve r, sockets that populate all 16 key pins must be allowed, so the circuit board must always provide for pins at all key pin locations. amd pin ah6 -- amd pin. amd socket a processors do not implement a pin at location ah6. all socket a designs must have a top plate or cover that blocks this pin location. when the cover plate blocks this loca- tion, a non-amd part (e.g., pga370) does not fit into the socket. however, socket manufacturers are allowed to have a contact loaded in the ah6 position. therefore, circuit board socket design should account for the possibility that a contact could be loaded in this position. the circuit board should treat the amd pin (ah6) as an nc pin. a socket designer has the option of creating a top mold piece that blocks this pin location. however, sockets that populate the amd pin must be allowed, so the circuit board must always provide for a nc type pin at this pin location. amd socket a processors do not implement a pin at location ah6. when a socket that does not pro- vide a pin hole at location ah6 is used, a non-amd pga370 part does not fit into socket a. analog pin aj13 -- analog pin. treat this pin as a nc. nc pins see table 2-2 on page 23 -- no connection pins (total of 71). the circuit board should pro- vide a plated hole for an nc pin. the pin hole should not be electri- cally connected to anything. 2.3.12 power, ground and compensation circuit connections signal name pin no . port description v cca aj23 -- power connection a. v cca is the processor pll supply. for infor- mation about the v cca pin, see table 5-2 "v cca electrical charac- teristics" on page 47 and the amd athlon? processor-based motherboard design guide (publication id 24363). v cc_core see table 2-2 on page 23 -- power connection (total of 101). v ss see table 2-2 on page 23 -- ground connection (total of 101). zn ac5 -- z negative and positive. these are the push-pull compensation circuit pins. in push-pull mode (selected by the sip (serial initializa- tion packet) parameter syspushpull asserted), zn is tied to v cc_core with a resistor that has a resistance matching the imped- ance z 0 of the transmission line. zp is tied to v ss with a resistor that has a resistance matching the impedance z 0 of the transmission line. zp ae5 --
32 amd geode? nx processors data book signal definitions 31177h
amd geode? nx processors data book 33 3 power management 31177h 3.0 power management this chapter describes the power management features of the amd geode? nx processor. the power management features of the processor are compliant with the acpi 1.0b and acpi 2.0 specifications and support amd powernow!? technology. 3.1 power management states the geode nx processor has a variety of operating states that support different power management goals. in addition to the standard operating state, the processor supports low-power halt and stop gran t states and the fid_change state. these states are used by advanced configuration and power interface (acpi) enabled operating systems, for processor power management. amd powernow! technol- ogy software is used to control processor performance states with operating systems that do not support acpi 2.0-defined processor perf ormance state control. figure 3-1 shows the power ma nagement states of the pro- cessor. the figure includes the acpi ?cx? naming conven- tion for these states. the sections that follow provide an overview of the power management states. for more details, refer to the amd athlon? processor system bus specification (publi- cation id 21902). note: in all power management states that the processor is powered, the system must not stop the system clock (sysclk/sysclk#) to the processor. figure 3-1. processor power management states c1 halt c0 working 4 execute hlt smi#, intr, nmi, init#, reset# incoming probe p r o b e s e r v i c e d stpclk# asserted s t p c l k # a s s e r t e d 2 s t p c l k # d e a s s e r t e d 3 c2 stop grant cache snoopable incoming probe probe serviced probe state 1 stpclk# deasserted (read plvl2 register or throttling) c3/s1 stop grant cache not snoopable sleep s t p c l k # a s s e r t e d s t p c l k # d e a s s e r t e d fid_change write to fidvidctl msr sip stream and system bus connect note: the system bus is connected during the following states: 1) the probe state 2) during transitions between the halt state and the c2 stop grant state 3) during transitions between the c2 stop grant state and the halt state 4) c0 working state software transitions hardware transitions legend
34 amd geode? nx processors data book power management 31177h 3.1.1 working state the working state is the state in which the processor is executing instructions. 3.1.2 halt state when the processor executes the hlt instruction, the pro- cessor enters the halt state and issues a halt special cycle to the amd processor system bus. the processor only enters the low power state di ctated by the clk_ctl msr (msr c001_001bh) if the system controller (northbridge) disconnects the amd processo r system bus in response to the halt special cycle. if stpclk# is asserted, the pr ocessor exits the halt state and enters the stop grant stat e. the processor initiates a system bus connect, if it is disconnected, then issues a stop grant special cycle. when stpclk# is de-asserted, the processor exits the stop grant state and re-enters the halt state. the processor issues a halt special cycle when reentering the halt state. the halt state is exited when the processor detects the assertion of init#, intr, nm i, reset#, or smi#, or via a local apic interrupt message. when the halt state is exited the processor initiates an amd processor system bus con- nect if it is disconnected. 3.1.3 stop grant states the processor enters the stop grant state upon recogni- tion of assertion of the stpclk# input. after entering the stop grant state, the processor issues a stop grant spe- cial bus cycle on the amd processor system bus. the pro- cessor is not in a low-power st ate at this time, because the amd processor system bus is st ill connected. after the northbridge disconnects the amd processor system bus in response to the stop grant special bus cycle, the proces- sor enters a low-power state di ctated by the clk_ctl msr (msr c001_001bh). if the northbridge needs to probe the processor during t he stop grant state wh ile the system bus is disconnected, it must firs t connect the system bus. con- necting the system bus places the processor into the higher power probe state. after the northbridge has com- pleted all probes of the processor, the northbridge must disconnect the amd processor system bus again so that the processor can return to the low-power state. during the stop grant states, the proce ssor latches init#, intr, nmi, smi#, or a local apic interrupt message if they are asserted. the stop grant state is exited upon the de-assertion of stpclk# or the assertion of reset#. when stpclk# is de-asserted, the processor in itiates a connect of the amd processor system bus if it is disconnect ed. after the processor enters the working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where stpclk# was initially recognized. if reset# is sampled asserted during the stop grant state, the pr ocessor exits the stop grant state and the reset process begins. there are two mechanisms for asserting stpclk#: hard- ware and software. the southbridge can force stpclk# assertion for throt- tling to protect the processo r from exceeding its maximum case temperature. typically this is accomplished by assert- ing the therm# input to the southbridge. throttling asserts stpclk# for a percentage of a predefined throt- tling period: stpclk# is repetitively asserted and de- asserted until therm# is de-asserted. software can force the processor into the stop grant state by accessing acpi-defined regi sters typically located in the southbridge. the operating system places the processor into the c2 stop grant state by reading the p_lvl2 register in the southbridge. if an acpi thermal zone is defined for the processor, the operating system can initia te throttling with stpclk# using the acpi defined p_cnt r egister in the southbridge. the northbridge connects the amd processor system bus, and the processor enters the probe state to service cache snoops during stop grant for c2 or throttling. in c2, probes are allowed, as shown in figure 3-1 on page 33. ? if an acpi thermal zone is defined for the processor, the operating system can in itiate thro ttling with stpclk# using the acpi defined p_cnt register in the southbridge. the northbridge connects the amd processor system bus, and the processor enters the probe state to service cache snoops during stop grant for c2 or throttling. ? the operating system places the processor into the c3 stop grant state by reading the p_lvl3 register in the southbridge. in c3, the operating system and north- bridge hardware enforce a policy that prevents the processor from being probe d. the southbridge de- asserts stpclk# and brings the processor out of the c3 stop grant state if a bus master request, interrupt, or any other enabled resume event occurs. ? the stop grant state is also entered for the s1, powered on suspend, system sleep state based on a write to the slp_typ and slp_en fields in the acpi-defined power management 1 control register in the southbridge. during the s1 sleep state, system soft- ware ensures no bus master or probe activity occurs. the southbridge de-asserts stpclk# and brings the processor out of the s1 stop grant state when any enabled resume event occurs.
amd geode? nx processors data book 35 power management 31177h 3.1.4 probe state the probe state is entered when the northbridge connects the amd processor system bus to probe the processor (for example, to snoop the processor caches) when the proces- sor is in the halt or stop gr ant state. when in the probe state, the processor responds to a probe cycle in the same manner as when it is in the working state. when the probe has been serviced, the processo r returns to the same state as when it entered the probe state (halt or stop grant state). when probe activity is completed the processor only returns to a low-power state after the northbridge discon- nects the amd processor system bus again. 3.1.5 fid_change state the fid_change state is part of the amd processor sys- tem bus fid_change protocol. during the fid_change state the frequency identification (fid[4:0]) code that determines the core frequency of the processor and volt- age identification (vid[4:0 ]) driven on the softvid[4:0] pins are transitioned to change the core frequency and core voltage of the processor. the nx 1750@14w proces- sor* supports multiple core voltages whereas the nx 1500@6w and nx 1250@6w processors* support only one core voltage (nx 1500@6w = 1.0v) (nx 1250@6w = 1.1v). note: the fid[3:0] pins of the processor do not transition as part of the fid_change protocol. 3.1.6 processor performance states and the fid_change protocol the fid_change protocol is used by amd powernow! software to transition the processor from one performance state to another. the fid_change protocol is also used for acpi 2.0-compliant processor performance state control. processor performance states are combinations of proces- sor core voltage and core frequency. processor perfor- mance states are used in embedded systems to optimize the power consumption of the processor (and therefore battery powered run-time) based upon processor utiliza- tion. table 5-4 "voltage and frequency combinations" on page 49. specifies the valid voltage and frequency combinations supported by the processor based upon the maximum core frequency and the maximum nominal core voltage. the core frequency multiplier is determined by a 5-bit fre- quency id (fid) code (msr c001_0041h[4:0]). the core voltage is determined by a 5-bit voltage id (vid) code (msr c001_0041h[12:8]). before pwrok is asserted to the processor, the vid[4:0] outputs of the processor dict ate the core voltage level of the processor. after pwrok is asserted, the core voltage of the proces- sor is dictated by the soft vid[4:0] outputs. the soft- vid[4:0] outputs of the processor are not driven to a deterministic value until after pwrok is asserted to the processor. the circuit board therefore must provide a ?vid multiplexer? to drive the vid[ 4:0] outputs to the dc/dc con- verter for the core voltage of the processor before pwrok is asserted and drive the so ftvid[4:0] outputs to the dc/dc converter after pwrok is asserted. the fid[3:0] signals are valid within 100 ns after pwrok is asserted. the chipset must not sample the fid[3:0] sig- nals until they become valid. for warm reset, the fid[3:0] signals become valid withi n 100 ns after reset# is asserted. for signal timing requirements refer to section 5.10 "signal and power-up requirements" on page 61. after reset# is de-asserted, the fid[3:0] outputs are not used to transmit fid information for subsequent software controlled changes in the operating frequency of the pro- cessor. processor performance state transitions are required to occur as two separate transitions. the order of these tran- sitions depends on whether the transition is to a higher or lower performance state. when transitioning from a lower performance state to a higher performance state the or der of the transitions is: 1) the fid_change protocol is used to transition to the higher voltage, while keeping the frequency fixed at the current setting. 2) the fid_change protocol is then used to transition to the higher frequency, while keeping the voltage fixed at the higher setting. when transitioning from a high performance state to a lower performance state the order of the transitions is: 1) the fid_change protocol is used to transition to the lower frequency, while keeping the voltage fixed at its current setting. 2) the fid_change protocol is then used to transition to the lower voltage, while keeping the frequency fixed at the lower setting. the processor provides two msrs to support the fid_change protocol: the fidvidctl msr (msr c001_0041h) and the fidvidstatus msr (msr c001_0042h). for a definition of these msrs and their use, refer to the bios requirements for amd powernow? technology application note (publication id 25264) *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w proces sor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark.
36 amd geode? nx processors data book power management 31177h 3.1.6.1 fid_change protocol example in any fid_change transition, only the core voltage or core frequency of the processor is transitioned. two fid_change transitions are required to transition the volt- age and frequency to a valid performance state. when the voltage is being transitioned, the frequency is held constant by transitioning to the same fid[3:0] as the current fid reported in the fidvidstatus msr (msr c001_0042h). example 1) system software determines that a change in proces- sor performance state is required. 2) system software execut es a wrmsr instruction to write to the fidvidctl msr (msr c001_0041h) to dic- tate: ? the new vid[4:0] code that will be driven to the dc/dc converter from the softvid[4:0] outputs of the processor that sele cts the new core voltage level. ? the new fid[4:0] code th at will be used by the processor to dictate its new operating frequency. ? a stop grant timeout count (sgtc[19:0], msr c001_0041h[51:32]) value that determines how many sysclk/sysclk# 133 mhz clock periods the processor will remain in the fid_change state. this time accounts for the time that it takes for the pll of the processor to lock to the new core frequency and the time that it takes for the core voltage of the processor to ramp to the new value. 3) the fidchgratio bit (msr c001_0041h[20]) must be set to 1. 4) the vidc bit (msr c001_0041h[17]) must be set to 1 if the voltage is going to be changed. 5) the fidc bit (msr c001_0041h[16]) must be set to 1 if the frequency is going to be changed. 6) writing the sgtc field (msr c001_0041h[51:32]) to a non-zero value initiates the fid_change protocol. on the instruction boundary that the sgtc field of the fidvidctl msr is written to a non-zero value, the processor stops code execution and issues a fid_change special cycle on the amd processor system bus. the fid_change special cycle has a data encoding of 0007_0002h that is passed on sdata[31:0]. sdata[36:32] contain the new fid[4:0] code during the fid_change special cycle. the northbridge is required to capture this fid[4:0] code when the fid_change special cycle is run. in response to receiving the fid_change special cycle, the northbridge is required to disconnect. the northbridge completes any in-progress bus cycles and then disable its arbiter before disconnecting the amd processor system bus so that it will not init iate a amd processor system bus connect based on bus master or other activity. the north- bridge must disconnect the amd processor system bus or the system will hang because the processor is not execut- ing any operating system or application code and is waiting for the amd processor system bus to disconnect so that it can continue with the fid_change protocol. the north- bridge initiates an amd processor system bus disconnect in the usual manner; it de-asserts connect. the processor allows the disconnect to complete by de- asserting procrdy. the northbridge completes the dis- connect by asserting clkfwdrst. once the amd processor system bus has been discon- nected in response to a fid_change special cycle, the northbridge is not allowed to initiate a re-connect, the pro- cessor is responsible for the eventual re-connect. after the amd processor system bus is disconnected, the processor enters a low-power state where the clock grid is ramped down by a value specified in the clk_ctl msr (msr c001_001bh). after entering the low-power state, the processor will: ? begin counting down the value that was programmed into the sgtc field. ? drive the new vid[4:0] value on softvid[4:0], causing its core voltage to transition. ? drive the new fid[4:0] value to its pll, causing the pll to lock to the new core frequency. when the sgtc count reaches zero, the processor ramps its entire clock grid to full frequency (the pll is already locked to) and signal that it is ready for the northbridge to transmit the new sip (serial initialization packet) stream associated with the new processor core operating fre- quency. the processor signals this by pulsing procrdy high and then low. the northbridge responds to this high pulse on procrdy by pulsing clkfwdrst low and then transferring a sip stream as it does after procrdy is de-asserted after the de-assertion of reset#. the difference is that the sip stream that the northbridge tr ansmits to the processor now corresponds to the fid[4:0] that was transmitted on sdata[36:32] during the fid_change special cycle. after the sip stream is transm itted, the processor initiates the amd processor system bus connect sequence by asserting procrdy. the northbridge responds by de- asserting clkfwdrst. the forward clocks are started and the processor issues a connect special cycle.
amd geode? nx processors data book 37 power management 31177h the amd processor system bu s connection causes the processor to resume execut ion of operating system and application code at the instruct ion that follows the wrmsr to the fidvidctl msr (msr c001_0041h) that started the fid_change protocol and processor performance state transition. figure 3-2 illustrates the pr ocessor softvid transition during the amd processor system bus disconnect in response to a fid_change special cycle. figure 3-2. softvid transition during the amd processor system bus disconnect for fid_change 1.4 v vcc_core 1.2 v softvid[4:0] from the processor vid combination that selects 1.2 v < 100 s procrdy connect clkfwdrst vid combination that selects 1.4 v the processor core frequency changes and new softvid[4:0] values are driven after the system bus interface disconnect occurs and the processor has entered a low power state. the duration of the disconnect is dictated by software programming the fidvidcontrol msr in the processor.
38 amd geode? nx processors data book power management 31177h 3.2 connect and disconnect protocol significant power savings of t he processor only occur if the processor is disconnected fr om the system bus by the northbridge while in the halt or stop grant state. the northbridge can optionally initiate a bus disconnect upon the receipt of a halt or stop grant special cycle. the option of disconnecting is controlled by an enable bit in the north- bridge. if the northbridge requires the processor to service a probe after the system bus has been disconnected, it must first initiate a system bus connect. 3.2.1 connect protocol in addition to the legacy stpclk# signal and the halt and stop grant special cycles, the amd processor system bus connect protocol includes the connect, procrdy, and clkfwdrst signals and a connect special cycle. amd processor system bus disconnects are initiated by the northbridge in response to the receipt of a halt, stop grant, or fid_change special cycle. reconnect is initiated by the processor in response to an interrupt for halt, stpclk# de-assertion, or completion of a fid_change transition. reconnect is initiated by the northbridge to probe the processor.the northbridge contains bios pro- grammable registers to enable the system bus disconnect in response to halt and stop grant special cycles. when the northbridge receives the halt or stop grant special cycle from the processor and, if there are no outstanding probes or data movements, the northbridge de-asserts connect a minimum of eigh t sysclk periods after the last command sent to the processor. the processor detects the de-assertion of co nnect on a rising edge of sysclk and de-asserts procrd y to the northbridge. in return, the northbridge asserts clkfwdrst in anticipa- tion of reestablishing a connection at some later point. note: the northbridge must disconnect the processor from the amd processor system bus before issu- ing the stop grant specia l cycle to the pci bus or passing the stop grant s pecial cycle to the south- bridge for systems that c onnect to the southbridge with hypertransport? technology. in response to halt spec ial cycles, the northbridge passes the halt special cycle to the pci bus or southbridge immediately. the processor can receive an interrupt after it sends a halt special cycle, or stpclk# de -assertion after it sends a stop grant special cycle to the northbridge but before the disconnect actually occurs. in this case, the processor sends the connect special cycle to the northbridge, rather than continuing with the disconnect sequence. in response to the connect special cycle, the northbridge cancels the disconnect request. the system is required to assert the connect signal before returning th e c-bit for the connect special cycle (assuming connect has been de-asserted). for more information, see the amd athlon? processor system bus specification (publication id 21902)for the def- inition of the c-bit and the connect special cycle. figure 3-3 shows stpclk# assertion resulting in the pro- cessor in the stop grant stat e and the amd processor sys- tem bus disconnected. figure 3-3. amd processor system bus disconnect sequence in the stop grant state stop grant stop grant stpclk# connect procrdy clkfwdrst pci bus system bus amd processor
amd geode? nx processors data book 39 power management 31177h an example of the amd processor system bus disconnect sequence is as follows: 1. the peripheral controller (southbridge) asserts stpclk# to place the processor in the stop grant state. 2. when the processor recognizes stpclk# asserted, it enters the stop grant stat e and then issues a stop grant special cycle. 3. when the special cycle is re ceived by the northbridge, it de-asserts connect, assuming no probes are pending, initiating a bus disconnect to the processor. 4. the processor responds to the northbridge by de- asserting procrdy. 5. the northbridge asserts clkfwdrst to complete the bus disconnect sequence. 6. after the processor is disconnected from the bus, the processor enters a low-power state. the northbridge passes the stop grant sp ecial cycle along to the southbridge. figure 3-4 shows the signal s equence of events that takes the processor out of the stop grant state, connects the processor to the amd processor system bus, and puts the processor into the working state. the following sequence of events removes the processor from the stop grant state and connects it to the system bus: 1) the southbridge de-asserts stpclk#, informing the processor of a wake event. 2) when the processor recognizes stpclk# de-asser- tion, it exits the low-power state and asserts procrdy, notifying the northbridge to connect to the bus. 3) the northbridge asserts connect. 4) the northbridge de-asserts clkfwdrst, synchro- nizing the forwarded clocks between the processor and the northbridge. the processor issues a connect special cycle on the sys- tem bus and resumes operat ing system and application code execution. figure 3-4. exiting the stop grant state and bus connect sequence stpclk# procrdy connect clkfwdrst
40 amd geode? nx processors data book power management 31177h 3.2.2 connect state diagram figure 3-5 and figure 3-6 on page 41 describe the northbridge and processor connect state diagrams, respectively. figure 3-5. northbridge connect state diagram condition 1 a disconnect is requested and probes are still pending. 2 a disconnect is requested and no probes are pending. 3 a connect special cycle from the processor. 4 no probes are pending. 5 procrdy is de-asserted. 6 a probe needs service. 7 procrdy is asserted. 8 three sysclk periods after clkfwdrst is de-asserted. although reconnected to the system interface, the north- bridge must not issue any non-nop sysdc commands for a minimum of four sysclk periods afte r de-asserting clkfwdrst . action a de-assert connect eight sysclk peri- ods after last sysdc sent. b assert clkfwdrst. c assert connect. d de-assert clkfwdrst. disconnect pending connect disconnect re q u e st e d reconnect pending probe pending 2 disconnect probe pending 1 1 3 2/ a 4/ a 5/ b 3/ c 7/ d,c 8 6/ c 7/ d 8 disconnect pending disconnect connect disconnect requested probe pending 2 reconnect pending probe pending 1 6/c 5/b 2/a 3/c 8 7/d,c 3 8 1 7/d 4/a
amd geode? nx processors data book 41 power management 31177h figure 3-6. processor connect state diagram condition 1 connect is de-asserted by the northbridge (for a pre- viously sent halt or st op grant special cycle). 2 processor receives a wake-up event and must cancel the disconnect request. 3 de-assert procrdy and slow down internal clocks. 4 processor wake-up event or connect asserted by northbridge. 5 clkfwdrst is de-asserted by the northbridge. 6 forward clocks start three sysclk periods after clkfwdrst is de-asserted. action a clkfwdrst is asserted by the northbridge. b issue a connect special cycle. (note 1) note 1. the connect special cycle is only issued af- ter a processor wake-up event (interrupt or stpclk# de-assertion) occurs. if the amd processor system bus is connected so the northbridge can probe the processor, a connect special cycle is not issued at that time (it is only issued after a subsequent pro- cessor wake-up event). c return internal clocks to full speed and assert procrdy. connect disconnect disconnect connect connect 1 3/a 4/c 5 6/b 2/b pending 2 pending 1 pending
42 amd geode? nx processors data book power management 31177h 3.3 clock control the processor implements a clock control (clk_ctl) msr (msr c001_001bh) that determines the internal clock divisor when the amd p rocessor system bus is dis- connected. refer to the amd geode? nx processors bios consider- ations application note (publication id 32483) and the bios requirements for bios requirements for amd pow- ernow? technology application note (publication id 25264) for more details on the clk_ctl register. 3.4 sysclk multipliers the processor provides two mechanisms for communicat- ing processor core operating frequency information to the northbridge. these are the proc essor fid[3:0] outputs and the fid_change special cycle. the fid[3:0] outputs spec- ify the core frequency of the processor as a multiple of the input clock (sysclk/sysclk#) of the processor. this processor supports an input clock, or front side bus (fsb), that runs up to 133 mhz. the fid[3:0] signals are valid after pwrok is asserted. the chipset must not sample the fid[3:0] signals until they become valid. the fid[3:0] ou tputs of the processor pro- vide processor operating frequency information the north- bridge uses when creating the sip stream the northbridge sends to the processor afte r reset# is de-asserted. the fid[3:0] outputs always select a 6x sysclk multiplier for the geode nx processor: fid[3:0] = 0110. software uses the fid_change protocol to transition the processor to the desired performance state. the fid[3:0] outputs are not used as part of the fid_change protocol and do not change from their reset# value during softwar e-controlled processor core frequency transitions. the fid_change special cycle is used to communicate processor operating frequency information to the north- bridge during software-controlled processor core voltage and frequency (performance state) transitions. the fidvidctl msr (msr c001_0041h) allows software to specify a 5-bit fid value during software-controlled proces- sor performance state transitions. the additional bit allows transitions to lower sysclk multipliers of 3x and 4x as well as all other sysclk multip liers supported by the pro- cessor. for a description of the fid_change protocol refer section 3.1.5 on page 35. table 3-1 lists the fid[4:0] sysclk multiplier codes for the processor used by software to dictate the core frequency of the processor and the 5-bit value driven on sdata[36:32]# by the processor during the fid_change special bus cycle. note: only clock multipliers associated with operating frequencies specified in section 5.0 "electrical specifications" on page 47 are valid for this pro- cessor. software distinguishes the speed grade of the processor by reading the mfid field of the fid- vidstatus msr (msr c001_0042h).
amd geode? nx processors data book 43 power management 31177h table 3-1. fid[4:0] sysclk multip lier combinations (note 1) fid[4:0] (note 2, note 3, note 4) clock mode sdata[36:32]# (note 5) fid[4:0] (note 2, note 3, note 4) clock mode sdata[36:32]# (note 5) 00000 11x 11111 10000 3x 01111 00001 11.5x 11110 10001 reserved reserved 00010 12x 11101 10010 4x 01101 00011 12.5x 11100 10011 reserved reserved 00100 5x 11011 10100 13x 11100 00101 5.5x 11010 10101 13.5x 11100 00110 6x 11001 10110 14x 11100 00111 6.5x 11000 10111 reserved reserved 01000 7x 10111 11000 15x 11100 01001 7.5x 10110 11001 reserved reserved 01010 8x 10101 11010 16x 11100 01011 8.5x 10100 11011 16.5x 11100 01100 9x 10011 11100 17x 11100 01101 9.5x 10010 11101 18x 11100 01110 10x 10001 11110 reserved reserved 01111 10.5x 10000 11111 reserved reserved note 1. on power up, the fid[3:0] pins are set to a clo ck multiplier value of 6x for the nx 1750@14w and nx 1500@6w processors* and 5x for the nx 1250@6w processor*. after re set, software is responsible for transitioning the pro- cessor to the desired frequency. note 2. value programmed into the fidvidctl msr (msr c001_0041h). note 3. the maximum fid that may be selected by softwa re is reported in the fidv idstatus msr (msr c001_0042h). note 4. bios initializes the clk_ctl msr (msr c001_001bh) dur ing the post routine to the desired value. the cpu id and implemented features such as powernow! and s2k bu s disconnect have implications to the appropriate value for this register. refer to the amd geode? nx processors bios considerations application note (publication id 32483) and the bios requirements for bios requirements for amd powernow? technology application note (publication id 25264) for more details on the clk_ctl register. note 5. value driven on sdata[36:32]# pins during the fid_ change special bus cycle. the sdata bus is active low, so the sdata[36:32]# values listed are what would be obse rved on the circuit board with a digital storage scope. *the amd geode nx 1750@14w processor operates at 1.4 ghz, the nx 150 0@6w processor operates at 1.0 ghz, and the nx 1250@6w process or operates at 667 mhz. model numbers reflect performance as described he re: http://www.amd.com/connectivitysolutions/geodenxbenchmark.
44 amd geode? nx processors data book power management 31177h 3.5 special cycles in addition to the specia l cycles documented in the amd athlon? processor system bus specification (publi- cation id 21902) the processor supports the smm enter, smm exit, and fid_ch ange special cycles. table 3-2 defines the contents of sdata[31:0] during the special cycles. table 3-2. processor special cycle definition special cycle contents of sdata[31:0] smm enter 0005_0002h smm exit 0006_0002h fid_change (note 1) note 1. the new fid[4:0] tak en from the fid[4:0] field of the fidvidctl msr (msr c001_0041h) is driven on sdata[36:32] during the fid_change special cycle. 0007_0002h
amd geode? nx processors data book 45 4 cpuid support 31177h 4.0 cpuid support the cpuid for the amd geode? nx processors is 681. the processor version and feature set recognition can be performed through the use of the cpuid instruction that provides complete information about the processor?ven- dor, type, name, etc., and its capabilities. software can make use of this information to accurately tune the system for maximum performance and benefit to users. for information on the use of the cpuid instruction see: ? amd athlon? and amd duron? processor recogni- tion application note addendum (publication id 21922) ? amd processor recognition application note (publica- tion id 20734)
46 amd geode? nx processors data book cpuid support 31177h
amd geode? nx processors data book 47 5 electrical specifications 31177h 5.0 electrical specifications this section provides information on electrical connections, absolute maximum ratings, and dc/ac characteristics for the amd geode? nx processor. all current specified as being sourced by the processor is negative . all current specified as being sunk by the processor is positive . 5.1 electrical connections 5.1.1 nc, amd, analog, and key pins the circuit board should provide a plated hole for a nc (no connect) pin (total of 71, see table 2-2 "pin assignment - sorted alphabetically by signal name" on page 23 for pin assignments). the pin hole should not be electrically con- nected to anything. the amd pin (pin ah6), analog pin (pin aj13) and key pins (total of 16, see tabl e 2-2 "pin assignment - sorted alphabetically by signal name" on page 23 for pin assign- ments) should be treated like a nc pin. see section 2.3.11 "key pin, amd pin, analog pin and no connect pins" on page 31 for more details regarding these pins. 5.1.2 decoupling see the amd athlon? processor-based motherboard design guide (publication id 24363) and amd geode? nx processors addendum to amd athlon? processor- based motherboard design guide (publication id 31860), or contact your local amd fae (field applications engi- neer) for information about the decoupling required on the circuit board for use with the geode nx processors. 5.2 absolute maximum ratings do not subject the processor to conditions that exceed the absolute ratings listed in table 5-1, as such conditions may adversely affect long-term reliab ility or result in functional damage. 5.3 v cca electrical characteristics v cca (pin aj23) is the processor pll supply. table 5-2 provides the voltage and current values for the v cca pin. table 5-1. absolute ratings symbol parameter min max v cc_core processor core supply ?0.5v v cc_core_nom + 0.5v v cca processor pll supply ?0.5v v cca_max + 0.5v t storage storage temperature of processor ?40oc 100oc table 5-2. v cca electrical characteristics symbol parameter min nom max units v vcca v cca voltage (note 1) 2.25 2.5 2.75 v i v vcca ? v cc_core i < 1.60v (note 2) -- i vcca v cca current (note 3) 0 50 ma/ghz note 1. minimum and maximum voltages are absolute. no transients below minimum nor above maximum voltages are permitted. note 2. for more inform ation, refer to the amd athlon? processor-based motherboard design guide (publication id 24363) and the amd geode? nx processors addendum to amd a thlon? processor-based motherboard design guide (publication id 31860) note 3. measured at 2.5v.
48 amd geode? nx processors data book electrical specifications 31177h 5.4 v cc_core electrical characteristics table 5-3 provides the electrical characteristics for v cc_core . figure 5-1 shows the processor core voltage (v cc_core ) waveform response to perturbation. the time t max_ac (positive ac transient excursion time) represents the maximum allowable time above the dc tolerance threshold. figure 5-1. v cc_core voltage waveform table 5-3. v cc_core electrical characteristics symbol parameter limit (note 1) units v cc_core_ac_max maximum excursion above v cc_core_nom (note 2) 150 mv v cc_core_dc_max maximum static voltage above v cc_core_nom (note 2) 100 mv v cc_core_min minimum voltage below v cc_core_nom (note 2) ?50 mv t max_ac maximum excursion time for ac transients 10 s note 1. all voltage measurements are taken differentially at the corefb/corefb# pins while the processor is in the working state. note 2. v cc_core nominal values and absolute minimum allowable v cc_core voltage for the geode nx processors is provided in table 5-4 "voltage and frequency combinations" on page 49. v cc_core_ac_max t max_ac v cc_core_dc_max v cc_core_nom v cc_core_min i core_min i core_max di /dt
amd geode? nx processors data book 49 electrical specifications 31177h 5.4.1 valid voltage and frequency combinations table 5-4 characterizes the valid voltage and frequency combinations for the amd g eode nx processor. the fre- quency column corresponds to the rated frequency of the processor. the maximum fid (mfid) field in the fidvid- status msr (msr c001_0042h[20:16]) is used by soft- ware to determine the maximum frequency of the processor. section 3.1 "power management states" on page 33 describes how amd powernow!? software uses this information to implement processor performance states table 5-4. voltage and frequency combinations amd geode? nx processor (note 1) v cc_core_nom voltag e (note 2, note 3) frequency (note 4) nx 1250@6w processor 1.10v (note 5) 667 mhz nx 1500@6w processor 1.00v (note 6) 1000 mhz nx 1750@14w processor 1.05v (note 7) 1000 mhz 1.10v 1067 mhz 1.15v 1133 mhz 1.20v 1200 mhz 1.25v 1400 mhz note 1. the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w processor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connecti vitysolutions/geodenxbenchmark. note 2. all voltages listed are nominal. see figure 5- 1 on page 48 for ac and dc transient voltage tolerances. note 3. the maximum processor die temperature is 95c for all voltage and frequency combinations. note 4. the ? ? symbol indicates that the bios v endor can use any performance state e qual to or less than the specified frequency at a given voltage. note 5. the absolute minimum voltage, inclusive of all tolerances and excursions, is 1.05v. note 6. the absolute minimum voltage, inclusive of all tolerances and excursions, is 0.95v. note 7. the absolute minimum voltage, inclusive of all tolerances and excursions, is 1.00v.
50 amd geode? nx processors data book electrical specifications 31177h 5.5 dc characteristics figure 5-2. sysclk and sysclk # differential clock signals table 5-5. sysclk and sysclk# dc characteristics (note 1) symbol parameter min max units v threshold-dc crossing before transition is detected (dc) 400 mv v threshold-ac crossing before transition is detected (ac) 450 mv i leak_p leakage current through p-channel pull up to v cc_core ?250 a i leak_n leakage current through n-channel pull down to v ss (ground) 250 a v cross differential signal crossover v cc_core /2 +/? 100 mv c pin capacitance (note 2) 25 pf note 1. the sysclk signal r epresents clkin and rstclk tied together while the sysclk# signa l represents clkin# and rstclk# tied together.) note 2. the sysclk and sysclk# signals have twice the listed capacitance because they conne ct to two input pads (i.e., clkin/rstclk and clkin#/rstclk#). v cross v threshold-dc = 400 mv v threshold-ac = 450 mv
amd geode? nx processors data book 51 electrical specifications 31177h . table 5-6. softvid[4:0] and vid[4:0] dc characteristics symbol parameter min max units i ol output current low 6 ma softvid_v oh softvid[4:0] output high voltage -- 2.625 (note 1) v | softvid_v oh ? v cc_core | < 1.60 (note 2) vid_v oh vid[4:0] output high voltage -- 5.25 (note 3) v note 1. the softvid pins must not be pu lled above 2.625v, which is 2.5v +5%. note 2. refer to the ?vcc_2.5v generation circuit? found in the ?motherboard required circuits,? section of the amd athlon? processor-based motherboard design guide (publication id 24363). note 3. the vid pins are either open circuit or pulled to gr ound. it is recommended that these pins are not pulled above 5.25v, which is 5.0v +5%. table 5-7. fid[3:0] dc characteristics symbol parameter min max units i ol output current low 6 ma v oh output high voltage -- 2.625 (note 1) v | v oh ? v cc_core | < 1.60v (note 2) note 1. the fid[3:0] pins must not be pulled above 2.625v, which is 2.5v +5%. note 2. refer to the ?vcc_2.5v generation circuit? found in the ?motherboard require d circuits? section of the amd athlon? processor-based motherboard design guide (publication id 24363).
52 amd geode? nx processors data book electrical specifications 31177h table 5-8. picd[1:0]# and picclk (apic pins) dc characteristics symbol parameter condition min max units v ih input high voltage (note 1) 1.7 2.625 (note 2) v v cc_core < v cc_core_max | v ih - v cc_core | 1.60v (note 3) v il input low voltage (note 1) -300 700 mv v oh output high voltage 2.625 (note 2) v v cc_core < v cc_core_max | v oh - v cc_core | 1.60v (note 3) v ol output low voltage -300 400 mv | leak_p tri-state leakage pull-up v in = v ss (ground) -1 ma | leak_n tri-state leakage pull-down v in = 2.5v 1 ma i ol output low current v ol max 9 ma c pin pin capacitance 4 12 pf note 1. characterized across dc supply voltage range. note 2. the 2.625v value is equal to 2.5v +5%. note 3. refer to vcc_2.5v generation circuit found in the motherboard required circuits, of the amd athlon? proces- sor-based motherboard design guide (publication id 24363).
amd geode? nx processors data book 53 electrical specifications 31177h table 5-9. amd processor system bus dc characteristics symbol parameter condition min max units v ref dc input reference voltage (note 1) (0.5 x v cc_core ) ? 50 (0.5 x v cc_core ) + 50 mv i vref_leak_p v ref tri-state leakage pull-up v in = v ref nominal ?100 a i vref_leak_n v ref tri-state leakage pull-down v in = v ref nominal 100 a v ih input high voltage 1.20v v cc_core (note 2) v ref + 200 v cc_core + 500 mv v cc_core < 1.20v (note 2) v ref + 100 v cc_core + 500 mv v il input low voltage 1.20v v cc_core (note 2) ?300 v ref ? 200 mv v cc_core < 1.20v (note 2) ?300 v ref ? 100 mv i leak_p tri-state leakage pull-up v in = v ss (ground) ?250 a i leak_n tri-state leakage pull-down v in = v cc_core nominal 250 a c in input pin capacitance 7 pf r on output resistance (note 3) 0.90 x r setn,p 1.1 x r setn,p r setp impedance set point, p channel (note 3) 40 70 r setn impedance set point, n channel (note 3) 40 70 note 1. v ref is nominally set to 50% of v cc_core with actual values that are specif ic to circuit board design implementa- tion. v ref must be created with a sufficiently accurate dc so urce and a sufficiently quiet ac response to adhere to the 50 mv specification listed above. note 2. the selection of a 1.2v break in the v ih and v il parameters is somewhat arbitrary, reflecting the need for tighter tolerances at lower voltage to maintain noise margin. note 3. measured at v cc_core /2.
54 amd geode? nx processors data book electrical specifications 31177h table 5-10. general dc characteristics symbol parameter condition min max units v ih input high voltage (note 1) (note 2) (note 3) 1.2v v cc_core 0.5 x v cc_core + 200 v cc_core + 300 mv v cc_core < 1.20v 0.5 x v cc_core + 100 v cc_core + 300 mv v il input low voltage (note 1) (note 2) (note 3) 1.2v v cc_core ?300 0.5 x v cc_core ? 200 mv v cc_core < 1.20v ?300 0.5 x v cc_core ? 100 mv v oh output high voltage (note 3) v cc_core ? 200 v cc_core + 300 mv v ol output low voltage (note 3) ?300 200 mv i leak_p tri-state leakage pull-up v in = v ss (ground) ?250 a i leak_n tri-state leakage pull-down v in = v cc_core nominal 250 a i oh output high current (note 4) ?6 ma i ol output low current (note 5) 6ma c pin pin capacitance 12 pf note 1. characterized across dc supply voltage range. note 2. the selection of a 1.2v break in the v ih and v il parameters is somewhat arbitrary, reflecting the need for tighter tolerances at lower voltages to maintain noise margin. note 3. values specified at nominal v cc_core . scale parameters between v cc_core_min and v cc_core_max . note 4. i ol and i oh are measured at v ol maximum and v oh minimum, respectively. note 5. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins.
amd geode? nx processors data book 55 electrical specifications 31177h 5.6 ac characteristics figure 5-3 shows a sample waveform. figure 5-3. sysclk waveform table 5-11. sysclk and sysclk # ac characteristics symbol parameter min @ max @ units clock frequency 50 133 50 133 mhz duty cycle 30% 30% 70% 70% t 1 period (note 1) (note 2) 10 7.5 ns t 2 high time 1.8 1.05 ns t 3 low time 1.8 1.05 ns t 4 fall time 2 2 ns t 5 rise time 2 2 ns period stability 300 300 ps note 1. circuitry driving the amd processor system bus clock i nputs must exhibit a suitably low closed-loop jitter bandwidth to allow the pll to track the jitter. the ?20 db attenuatio n point, as measured into a 10 or 20 pf load must be less than 500 khz. note 2. circuitry driving the amd processor system bus cl ock inputs may purposely alte r the amd processor system bus clock frequency (spread spectrum clo ck generators). in no cases can the amd processor system bus period violate the minimum specification above. amd pro cessor system bus clock inputs can va ry from 100% of the specified fre- quency to 99% of the specified frequency at a maximum rate of 100 khz. t 5 v cross t 2 t 3 t 4 t 1 v threshold-ac
56 amd geode? nx processors data book electrical specifications 31177h table 5-12. picd[1:0]# and picclk (apic pins) ac characteristics symbol parameter min max units t rise signal rise time (note 1) 1.0 3.0 v/ns t fall signal fall time (note 1) 1.0 3.0 v/ns t su setup time 1 ns t hd hold time 1 ns note 1. edge rates indicate the range for characterizing the inputs. table 5-13. amd processor system bus ac characteristics group note 1 symbol parameter min max units all signals (note 2) t rise output rise slew rate 1 3 v/ns t fall output fall slew rate 1 3 v/ns forward clocks t skew-diffedge (note 3) output skew with respect to a dif- ferent clock edge ?770ps t su (note 4) input data setup time 300 ps t hd (note 4) input data hold time 300 ps c in capacitance on input clocks 3 7 pf c out capacitance on output clocks 4 7 pf sync t val (note 5) (note 6) rstclk to output valid 250 2000 ps t su (note 5) (note 7) setup to rstclk 500 ps t hd (note 5) (note 7) hold from rstclk 1000 ps note 1. the parameters are grouped based on the s ource or destination of the signals involved. note 2. rise and fall time ranges are guidelines over which the i/o has been characterized. note 3. t skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at th e package, with respect to different clock edges. note 4. input su and hd times are with respect to the appropriate clock forward group input clock. note 5. the synchronous signals incl ude procrdy, connect, and clkfwdrst. note 6. t val is rstclk rising edge to output valid for procrdy . measure the signal at the receiver end of a 50 ohm trace. subtract the delay effect of the transmission line. note 7. t su is setup of connect/clkfwdrst to rising edge of rstclk. t hd is hold of connect/clkfwdrst from rising edge of rstclk.
amd geode? nx processors data book 57 electrical specifications 31177h table 5-14. general ac characteristics symbol parameter min max units t su sync input setup time (note 1) (note 2) 2.0 ns t hd sync input hold time (note 1) (note 2) 0.0 ps t delay output delay with respect to rstclk (note 2) 0.0 6.1 ns t bit input time to acquire (note 3) (note 4) 20.0 ns t rpt input time to reacquire (note 5) (note 6) (note 7) (note 8) 40.0 ns t rise signal rise time (note 9) 1.0 3.0 v/ns t fall signal fall time (note 9) 1.0 3.0 v/ns t valid time to data valid (note 10) 100 ns note 1. these are aggregate numbers. note 2. edge rates indicate the range over which inputs were characterized. note 3. this value assumes rstclk frequency is 10 ns ==> tbit = 2 x f rst . note 4. the approximate value for standard case in normal mode operation. note 5. this value is dependent on rstclk frequen cy, divisors, low power mode, and core frequency. note 6. re-assertions of the signal within this time are not guaranteed to be seen by the core. note 7. this value assumes that the skew between rstclk and k7clkout is much less than one phase. note 8. this value assumes rstclk and k7clkout are runn ing at the same frequency, t hough the processor is capable of other configurations. note 9. in asynchronous operation, the signal mu st persist for this time to enable capture. note 10. time to valid is for any open-drain pins. see require ments 7 and 8 of section 5.10. 1.1 "signal sequence and timing description" on page 61 for more information.
58 amd geode? nx processors data book electrical specifications 31177h 5.7 open-drain test circuit figure 5-4 is a test circuit that may be used on automated test equipment (ate) to test for validity on open-drain pins. figure 5-4. general ate open-drain test circuit 5.8 fid_change induced pll lock time table 5-15 shows the time required for the pll of the pro- cessor to lock at the ne w frequency specified in a fid_change transition. software must program the sgtc field of the fidvidctl msr (msr c001_0041h) to produce a fid_change dura- tion equal to or greater than the fid_change induced pll lock time. for more information about the fid_change protocol, see section 3.1 "power management states" on page 33. note 1. v termination = 1.2 v for vid and fid pins v termination = 1.0 v for apic pins note 2. i ol = ?6 ma for vid and fid pins i ol = ?9 ma for apic pins i ol = output current (note 2) v termination (note 1) 50 3% open-drain pin table 5-15. fid_change induced pll lock time parameter max units fid_change induced pll lock time 50 s
amd geode? nx processors data book 59 electrical specifications 31177h 5.9 thermal diode characteristics the amd geode? nx processor provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor. the diode anode (thermda) and cathode (thermdc) are available as pins on the processor. refer to section 2.3.8 "thermal diode interface signals" on page 28 for more details. 5.9.1 thermal diode electrical characteristics table 5-16 shows the processor electrical characteristics of the on-die thermal diode. 5.9.2 thermal protection characterization the following section describes parameters relating to thermal protection. the implem entation of thermal control circuitry to control processor te mperature is left to the man- ufacturer to determine how to implement. thermal limits in circuit board design are necessary to pro- tect the processor from thermal damage. t shutdown is the temperature for thermal protection circuitry to initiate shut- down of the processor. t sd_delay is the maximum time allowed from the detection of the over-temperature condi- tion to processor shutdown to prevent thermal damage to the processor. systems that do not implement thermal protection circuitry or that do not react within the time specified by t sd_delay can cause thermal damage to the processor during a fan failure or if the processor is powered up without a heat- sink. the processor relies on thermal circuitry on the circuit board to turn off the regulated core voltage to the proces- sor in response to a thermal shutdown event. thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents: ? amd athlon? processor-based motherboard design guide (publication id 24363) ? amd thermal, mechanical, and chassis cooling design guide (publication id 23794) table 5-17 shows the t shutdown and t sd_delay specifi- cations necessary for circuitry in circuit board design for thermal protection of the processor. table 5-16. thermal diode electrical characteristics symbol parameter min nom max units i sourcing current (note 1) 5 300 a n f, lumped lumped ideality factor (note 2) (note 3) (note 4) 1.00000 1.00374 1.00900 n f, actual actual ideality factor (note 3) (note 4) 1.00261 r t series resistance (note 3) (note 4) 0.93 ohms note 1. the sourcing current should always be used in forward bias only. note 2. characterized at 95c with a forward bias current pair of 10 a and 100 a. amd recommends using a minimum of two sourcing currents to accurately meas ure the temperature of the thermal diode. note 3. not 100% tested. specified by design and limited characterization. note 4. the lumped ideality factor adds the effect of the series resistance term to the actual ideality factor. the series re- sistance term indicates the resistance from the pins of th e processor to the on-die thermal diode. the value of the lumped ideality factor depends on the sourcing current pair used. table 5-17. guidelines for platform thermal protection of the processor symbol parameter (note 1) (note 2) (note 3) max units t shutdown thermal diode shutdown temperature for processor protection 125 c t sd_delay maximum allowed time from t shutdown detection to processor shutdown 500 ms note 1. the thermal diode is not 100% tested, it is specified by design and limited characterization. note 2. the thermal diode is capable of responding to thermal events of 40c/s or faster. note 3. the geode nx processor provides a thermal diode for measuring die temperature of the processor. the processor relies on thermal circuitry on the circuit board to turn off the regulated core voltage to the processor in response to a thermal shutdown event. refer to amd athlon? processor-based motherboard design guide (publication id 24363) for thermal protection circuitry designs.
60 amd geode? nx processors data book electrical specifications 31177h 5.9.3 part-specific thermal po wer performance specifications the tables in this section specify the part-specific therma l power performance specificatio ns for the geode nx processor. this includes the nominal dc operating voltage of the proc essor core in the c0 working state and the stop grant state. table 5-18. thermal power pe rformance specifications frequency in mhz v cc_core (core voltage) thermal power max maximum die temperature working state c0 (note 1) note 1. see figure figure 3-1 "processor power management states" on page 33. stop grant c3/s1 (note 1) (note 2) note 2. power measurements are at 50 0 mhz and 1.05v.the amd pro cessor system bus is disconnected and has a low power ratio of 1/64 for stop grant disconnect and a low powe r ratio of 1/64 halt disconnect applied to the core clock grid of the processor. amd geode? nx 1250@6w processor (note 3) note 3. the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w processor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connecti vitysolutions/geodenxbenchmark. 667 1.10v 9.0w (note 4) (6.0w typical) note 4. thermal design power represents the maximum sustaine d power dissipated while executing publicly-available soft- ware or instruction sequences under normal system operation at nominal v cc_core . thermal solutions must mon- itor the temperature of the processo r to prevent the processor from ex ceeding its maximum die temperature. 3.0w 95c amd geode? nx 1500@6w processor (note 3) 1000 1.00v 9.0w (note 4) (6.0w typical) 3.0w 95c amd geode? nx 1750@14w processor (note 3) 1400 1.25v 25.0w (note 4) (14.0w typical) 3.0w 95c
amd geode? nx processors data book 61 electrical specifications 31177h 5.10 signal and powe r-up requirements this chapter describes the amd geode? nx processor?s power-up requirements duri ng system power-up and warm resets. 5.10.1 power-up requirements 5.10.1.1 signal sequence and timing description figure 5-5 shows the relationship between key signals in the system during a power-up s equence. this figure details the requirements of the processor. note: figure 5-5 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. the signal timing requirements for figure 5-5 are as fol- lows: 1) reset# must be asserted before pwrok is asserted. the geode nx processor does not set the correct clock multiplier if pwrok is asserted prior to a reset# assertion. it is recommended that reset# be asserted at least 10 ns prior to the assertion of pwrok. in practice, a southbrid ge asserts reset# millisec- onds before pwrok is asserted. 2) all circuit board voltage planes must be within specifi- cation before pwrok is asserted. pwrok is an output of the voltage regulation circuit on the circuit board. pwrok indicates that v cc_core and all other voltage plane s in the system are within specification. the circuit board is required to delay pwrok asser- tion for a minimum of three milliseconds from the 3.3v supply being within specificat ion. this delay ensures that the system clock (sysc lk/sysclk#) is operat- ing within specification when pwrok is asserted. the processor core voltage, v cc_core , must be within specification before pwrok is asserted as dictated by the vid[4:0] pins stra pped on the processor pack- age. before pwrok assertion, the processor is clocked by a ring oscillator. before pwrok is asserted, the softvid[4:0] outputs of the processor are not driven to a deterministic value. the processor drives the softvid[4:0] outputs to the same value as dictated by the vid[4:0] pins within 20 ns of pwrok assertion. figure 5-5. signal relationship requirements during power-up sequence 2 1 3 4 5 6 7 8 3.3 v supply v cca (2.5 v) v cc_core (processor core) (for pll) reset# nb_reset# pwrok fid[3:0] system clock warm reset condition
62 amd geode? nx processors data book electrical specifications 31177h the processor pll is powered by v cca . the proces- sor pll does not lock if v cca is not high enough for the processor logic to switch for some period before pwrok is asserted. v cca must be within specifica- tion at least 5 s before pwrok is asserted. in practice v cca , v cc_core , and all other voltage planes must be within specification for several milli- seconds before pwrok is asserted. after pwrok is asserted, the processor pll locks to its operational frequency. 3) the system clock (sysclk/sysclk#) must be run- ning before pwrok is asserted. when pwrok is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the pll. the reference system clock must be valid at this time. the system clocks are designed to be running after 3.3v has been within specification for 3 ms. 4) pwrok assertion to de-assertion of reset#. the duration of reset# asse rtion during cold boots is intended to satisfy the time it takes for the pll to lock with a less than 1 ns phase error. the processor pll begins to run after pwrok is asserted and the inter- nal clock grid is switched from the ring oscillator to the pll. the pll lock time may take from hundreds of nanoseconds to tens of microseconds. it is recom- mended that the minimum time between pwrok assertion to the de-asserti on of reset# be at least 1.0 ms . southbridge enforces a delay of 1.5 to 2.0 ms between pwrgd (southbridge version of pwrok) assertion and nb_r eset# de-assertion. 5) pwrok must be monotonic and meet the timing requirements as defined in table 5-14 "general ac characteristics" on page 57. the processor should not switch between the ring oscillator and the pll after the initial assertion of pwrok. 6) nb_reset# must be asserted (causing connect to also assert) before reset# is de-asserted. in practice all southbridge enforces this requirement. if nb_reset# does not asse rt until after reset# has de-asserted, the processo r misinterprets the con- nect assertion (due to nb_reset# being asserted) as the beginning of the sip (serial initialization packet) transfer. there must be sufficient overlap in the resets to ensure th at connect is sampled asserted by the processor before reset# is de- asserted. 7) the fid[3:0] signals are valid within 100 ns after pwrok is asserted. the chip set must not sample the fid[3:0] signals until they become valid. refer to the amd athlon? processor-based motherboard design guide (publication id 24363) for the specific imple- mentation and additional circuitry required. 8) the fid[3:0] signals becom e valid within 100 ns after reset# is asserted . refer to the amd athlon? pro- cessor-based motherboard design guide (publication id 24363) for the specific implementation and addi- tional circuitry required. 5.10.1.2 clock multiplier selection (fid[3:0]) the chipset samples the fid[3: 0] signals in a chipset-spe- cific manner from the processor and uses this information to determine the correct sip. the chipset then sends the sip information to the proce ssor for configuration of the amd processor system bus for the clock multiplier that determines the processor frequency indicated by the fid[3:0] code. the sip is sent to the processor using the sip protocol. this protocol uses the procrdy, con- nect, and clkfwdrst signals, that are synchronous to sysclk. for more information, see section 2.3.7 "frequency id interface signals" on page 28. 5.10.1.3 serial initialization packet (sip) protocol refer to amd athlon? processor system bus specifica- tion (publication id 21902) for details of the sip protocol. 5.10.2 processor warm reset requirements processor and northbridge reset pins reset# cannot be asserted to the processor without also being asserted to the northb ridge. reset# to the north- bridge is the same as pci reset#. the minimum asser- tion for pci reset# is 1 ms. southbridge enforces a minimum assertion of reset# for the processor, north- bridge, and pci of 1.5 to 2.0 ms.
amd geode? nx processors data book 63 6 mechanical data 31177h 6.0 mechanical data the amd geode? nx processo r connects to the mother- board through a pin grid array (pga) socket named socket a. this processor utilizes the organic pin grid array (opga) package type described in this chapter. for more information, see the amd athlon? processor-based moth- erboard design guide (publication id 24363). 6.1 die loading the processor die on the opga package is exposed at the top of the package. this feat ure facilitates heat transfer from the die to an approved heat sink. any heat sink design should avoid loads on corners and edges of die. the opga package has compliant pads that serve to bring sur- faces in planar contact. tool -assisted zero insertion force sockets should be designed so that no load is placed on the substrate of the package. table 6-1 shows the mechanical loading specifications for the processor die. it is critical that the mechanical loading of the heat sink does not exceed the limits shown in table 6-1. 6.2 opga package descriptions table 6-2 shows the part number 28104 opga package dimensions in millimeters assigned to the letters and sym- bols used in the package diagram, figure 6-1 on page 64. table 6-1. mechanical loading location dynamic (max) static (max) units die surface (note 1) note 1. load specified for coplanar contact to die surface. 100 30 lbf die edge (note 2) note 2. load defined for a surface at no more than a two- degree angle of inclination to die surface. 10 10 lbf table 6-2. 28104 opga package dimensions letter or symbol min dimension (note 1) max dimension (note 1) letter or symbol min dimension (note 1) max dimension (note 1) d/e 49.27 49.78 g/h ? 4.50 d1/e1 45.72 bsc a 1.917 ref d2 7.47 ref a1 0.977 1.177 d3 3.30 3.60 a2 0.80 0.88 d4 10.78 11.33 a3 0.116 ? d5 10.78 11.33 a4 ? 1.90 d6 8.13 8.68 p?6.60 d7 12.33 12.88 b0.430.50 d8 3.05 3.35 b1 1.40 ref d9 12.71 13.26 s 1.435 2.375 e2 11.33 ref l 3.05 3.31 e3 2.35 2.65 m 37 e4 7.87 8.42 n 453 e5 7.87 8.42 e 1.27 bsc e6 10.73 11.28 e1 2.54 bsc e8 13.28 13.83 mass (note 2) 11.0 g ref e9 1.66 1.96 note 1. dimensions are given in millimeters. note 2. the mass consists of the completed package, including processor, surface mounted parts, and pins.
64 amd geode? nx processors data book mechanical data 31177h figure 6-1. 28104 opga package outline
amd geode? nx processors data book 65 7 ordering information 31177h *the amd geode? nx 1750@14w processor operates at 1.4 ghz, the nx 1500@6w processor operates at 1.0 ghz, and the nx 1250@6w proces sor operates at 667 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark. 7.0 ordering information ordering information for the amd geode? nx processor is cont ained in this section. the ordering part number (opn) is formed by a combination of the elements shown in figure 7-1 below. this opn is given as an example only. figure 7-1. opn for the amd geode? nx processors opn (note 1) family/architecture: anx = amd athlon-based geode solution model number: nx 1250@6w* operates at 667 mhz nx 1500@6w* operates at 1000 mhz nx 1750@14w* operates at 1400 mhz maximum thermal design power (tdp): l = 9 watt s = 25 watt package type: f = opga max die temperature: m = 95oc eutectic f = 95oc lead reduced system bus speed: c = 266 fsb (133 mhz) size of l2 cache: 3 = 256 kb operating voltage: g = 1.0v x = 1.25v y = 1.10v note 1. spaces are added to the ordering number shown above for viewing clarity only. anx l 1500 f g c 3 f table 7-1. valid opn combinations family/architecture base model no. fsb/cache max die temperature anx l1250fy c3 m l1500fg s1750fx anx l1250fy c3 f l1500fg s1750fx note: consult your local amd sales office to c onfirm availability of specific valid co mbinations and to check on newly released combinations possibly not listed.
66 amd geode? nx processors data book ordering information 31177h
a appendix a: thermal diode calculations 31177h amd geode? nx processors data book 67 appendix a supporting documentation a.1 thermal diode calculations this section contains informat ion about the calculations for the on-die thermal diode of the amd geode? nx proces- sor. for electrical information about this thermal diode, see table 5-16 "thermal diode electrical characteristics" on page 59. a.1.1 ideal diode equation the ideal diode equation uses the variables and constants defined in table a-1. equation 1 shows the ideal diode calculation. equation 1. sourcing two currents and using equation 1 derives the dif- ference in the base-to-emitter voltage that leads to finding the diode temperature as shown in equation 2. the use of dual sourcing currents allows the measurement of the ther- mal diode temperature to be more accurate and less sus- ceptible to die and process revisions. temperature sensors that utilize series resistance cancellation can use more than two sourcing currents and are suitable to be used with the amd thermal diode. equation 2 is the formula for calcu- lating the temperature of a thermal diode. equation 2. a.1.2 temperature offset correction a temperature offset may be required to correct the value measured by a temperature sensor. an offset is necessary if a difference exists between the lumped ideality factor of the processor and the ideality factor assumed by the tem- perature sensor. the lumped ideality factor can be calcu- lated using the equations in this section to find the temperature offset that sh ould be used with the tempera- ture sensor. table a-2 shows the constants and variables used to calcu- late the temperature offset correction. table a-1. constants and variables for the ideal diode equation equation symbol variable, constant description n f, lumped lumped ideality factor k boltzmann constant q electron charge constant t diode temperature (kelvin) v be voltage from base to emitter i c collector current i s saturation current v be n flumped , k q -- - t i c i s --- - ?? ?? ln ??? = table a-2. temperature offset equation constants and variables equation symbol variable, constant description n f, actual actual ideality factor n f, lumped lumped ideality factor n f, ts ideality factor assumed by temperature sensor i high high sourcing current i low low sourcing current t die, spec die temperature specification t offset temperature offset t v be high , v be low , ? n f lumped , k q -- - i high i low ------- - ?? ?? ln ?? ----------------------------------------------------------------- =
68 amd geode? nx processors data book appendix a: thermal diode calculations 31177h the formulas in equation 3 and equation 4 can be used to calculate the temperature offs et for temperature sensors that do not employ series resistance cancellation. the result is added to the value measured by the temperature sensor. contact the vendor of the temperature sensor being used for the value of n f,ts . refer to the document, on-die thermal diode characterization (publication id 25443) for further details. equation 3 shows the equation for calculating the lumped ideality factor (n f, lumped ) in sensors that do not employ series resistance cancellation. equation 3. equation 4 shows the equation for calculating temperature offset (t offset ) in sensors that do not employ series resis- tance cancellation. equation 4. equation 5 is the temperature offset for temperature sen- sors that utilize series resistance cancellation. add the result to the value measured by the temperature sensor. note that the value of n f,ts in equation 5 may not equal the value used in equation 4. equation 5. f lumped , n factual , = r t i high i low ? () ? k q -- - t die spec , 273.15 + () i high i low ------- - ?? ?? ln ? --------------------- --------------------- ------------------ -------------- + t offset t die spec , 273.15 + () =1 n f lumped , n fts , ---------------- ? ?? ?? ? t offset t die spec , 273.15 + () =1 n f actual , n fts , ---------------- ? ?? ?? ?
amd geode? nx processors data book 69 appendix a: conventions, abbreviations, and references 31177h a.2 conventions, abbreviations, and references this section contains inform ation about the conventions and abbreviations used in this document. a.2.1 signals and bits ? active-low signals?signal names containing a pound sign, such as sfillvalid#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. when used in this context, high and low are wr itten with an initial upper case letter. ? signal ranges?in a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (f or example, d[63:0]). ? reserved bits and signals?signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. these bits and signals are reserved by amd for future implementations. when software reads register s with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. ? three-state?in timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. ? invalid and don?t-care?in timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. a.2.2 data terminology the following list defines data terminology: ? quantities ?a word is two bytes (16 bits) ?a doubleword is four bytes (32 bits) ?a quadword is eight bytes (64 bits) ? an octaword is 16 bytes (128 bits) ? a cache line is eight quadwords (64 bytes) ? addressing?memory is addressed as a series of bytes on 8-byte (64-bit) boundaries in which each byte can be separately enabled. ? abbreviations?the following notation is used for bits and bytes: ? kilo (k, as in 4-kbyte page) ? mega (m, as in 4 mbits/sec) ? giga (g, as in 4 gbytes of memory space) see table a-3 for more abbreviations. ? little-endian convention?the byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left?the little end is on the right and the big end is on the left. data structure diagrams in memory show low addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. ? bit ranges?in text, bit ranges are shown with brackets and a colon (for example, bits [9:1]). the same applies for signal or bus names. the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, ad[31:0]). ? bit values?bits can either be set to 1 or cleared to 0. ? hexadecimal and binary numbers?unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. a.2.3 abbreviations and acronyms table a-3 contains the definitions of abbreviations used in this document. table a-3. definitions of abbreviations abbreviation meaning a ampere ffarad g giga? gb gigabit gb gigabyte h henry h hexadecimal kkilo? kb kilobyte m mega? mb megabit mb megabyte mhz megahertz m milli? ms millisecond mw milliwatt micro? a microampere f microfarad s microsecond v microvolt n nano? na nanoampere ns nanosecond ohm ohm ppico? pf picofarad ph picohenry ps picosecond s second vvolt wwatt
70 amd geode? nx processors data book appendix a: conventions, abbreviations, and references 31177h table a-4 contains the defini tions of acronyms that may have been used in this document. a.2.4 web sites and support ? www.amd.com other web sites of interest include the following: ? jedec home page?www.jedec.org ? ieee home page?www.computer.org ? agp forum?www.agpforum.org table a-4. definitions of acronyms acronyms meaning acpi advanced configuration and power interface agp accelerated graphics port apci agp peripheral component interconnect api application programming interface apic advanced programmable interrupt controller bios basic input/output system bist built-in self-test biu bus interface unit cpga ceramic pin grid array ddr double-data rate dimm dual inline memory module dma direct memory access dram direct random access memory eide enhanced integrated device electronics eisa extended industry standard architecture eprom enhanced programmable read only memory fifo first in, first out fsb front side bus gart graphics address remapping table hstl high-speed transistor logic ide integrated device electronics isa industry standard architecture jedec joint electron device engineering council jtag joint test action group lan large area network lru least-recently used lvttl low voltage transistor to transistor logic msb most significant bit mux multiplexer nmi non-maskable interrupt od open-drain opga organic pin grid array pga pin grid array pa physical address pci peripheral component interconnect pde page directory entry pdt page directory table pll phase locked loop pmsm power management state machine pos power-on suspend post power-on self-test ram random access memory rom read only memory rxa read acknowledge queue sdi system dram interface sdram synchronous direct random access memory sip serial initialization packet smbus system management bus spd serial presence detect sram synchronous random access memory srom serial read only memory tlb translation lookaside buffer tom top of memory ttl transistor to transistor logic vas virtual address space vpa virtual page address vga video graphics adapter usb universal serial bus zdb zero delay buffer acronyms meaning
amd geode? nx processors data book 71 appendix a: revision history 31177h a.3 revision history this document is a report of the revision/creation process of the data book for the amd geode? nx processor. any revi- sions (i.e., additions, deletions, parameter correct ions, etc.) are recorded in the table(s) below. table a-5. revision history date revision description may 2004 a initial release september 2004 b see revision b for details. october 2004 c removed ?preliminary? label and changed ?leadfree? to ?lead reduced? march 2005 d corrected information in notes for tables 6-2 and 8-2 concerning minimum voltage. june 2005 e major addition was adding apic interface. see revision e for details. september 2005 f big re-write / organizational layout changes. see revision f for details. march 2006 g updated mechanical data section wit h 28104 opga package dimensions and incor- porated other minor edits. april 2006 h updated section 7.0 "ordering info rmation" on page 65 with three new opns: ANXL1250FYC3F, anxl1500fgc3f, and anxs1750fxc3f. an f in the last char- acter of the order number means 95oc lead reduced.
one amd place ? p.o. box 3453 ? sunnyvale, ca 94088-3453 usa ? tel: 408-749-4000 or 800-538-8450 ? twx: 910-339-9280 ? telex: 3 4-6306 www.amd.com

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